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[AVX-512] Replace get512BitSuperRegister with calls to TargetRegisterInfo::getMatchingSuperReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282359 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4816,8 +4816,11 @@ void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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// If this an extended register and we don't have VLX we need to use a
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// 512-bit move.
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Opc = X86::VMOVAPSZrr;
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DestReg = get512BitSuperRegister(DestReg);
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SrcReg = get512BitSuperRegister(SrcReg);
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
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&X86::VR512RegClass);
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SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
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&X86::VR512RegClass);
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}
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} else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
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if (HasVLX)
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@ -4828,8 +4831,11 @@ void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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// If this an extended register and we don't have VLX we need to use a
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// 512-bit move.
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Opc = X86::VMOVAPSZrr;
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DestReg = get512BitSuperRegister(DestReg);
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SrcReg = get512BitSuperRegister(SrcReg);
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
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&X86::VR512RegClass);
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SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
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&X86::VR512RegClass);
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}
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} else if (X86::VR512RegClass.contains(DestReg, SrcReg))
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Opc = X86::VMOVAPSZrr;
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@ -691,13 +691,3 @@ X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
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FrameReg = getX86SubSuperRegister(FrameReg, 32);
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return FrameReg;
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}
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unsigned llvm::get512BitSuperRegister(unsigned Reg) {
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if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
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return X86::ZMM0 + (Reg - X86::XMM0);
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if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
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return X86::ZMM0 + (Reg - X86::YMM0);
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if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
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return Reg;
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llvm_unreachable("Unexpected SIMD register");
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}
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@ -137,9 +137,6 @@ public:
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unsigned getSlotSize() const { return SlotSize; }
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};
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//get512BitRegister - X86 utility - returns 512-bit super register
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unsigned get512BitSuperRegister(unsigned Reg);
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} // End llvm namespace
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#endif
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