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[X86][SSE] Float comparisons can sometimes be safely commuted
For ordered, unordered, equal and not-equal tests, packed float and double comparison instructions can be safely commuted without affecting the results. This patch checks the comparison mode of the (v)cmpps + (v)cmppd instructions and commutes the result if it can. Differential Revision: http://reviews.llvm.org/D7178 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227145 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim
parent
b9a39da95e
commit
44513da617
@ -2701,6 +2701,30 @@ X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
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MI->getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
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return TargetInstrInfo::commuteInstruction(MI, NewMI);
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}
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case X86::CMPPDrri:
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case X86::CMPPSrri:
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case X86::VCMPPDrri:
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case X86::VCMPPSrri:
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case X86::VCMPPDYrri:
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case X86::VCMPPSYrri: {
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// Float comparison can be safely commuted for
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// Ordered/Unordered/Equal/NotEqual tests
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unsigned Imm = MI->getOperand(3).getImm() & 0x7;
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switch (Imm) {
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case 0x00: // EQUAL
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case 0x03: // UNORDERED
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case 0x04: // NOT EQUAL
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case 0x07: // ORDERED
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if (NewMI) {
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MachineFunction &MF = *MI->getParent()->getParent();
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MI = MF.CloneMachineInstr(MI);
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NewMI = false;
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}
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return TargetInstrInfo::commuteInstruction(MI, NewMI);
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default:
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return nullptr;
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}
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}
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case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
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case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
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case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
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@ -2799,6 +2823,26 @@ bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
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SrcOpIdx1 = 1;
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SrcOpIdx2 = 2;
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return true;
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case X86::CMPPDrri:
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case X86::CMPPSrri:
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case X86::VCMPPDrri:
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case X86::VCMPPSrri:
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case X86::VCMPPDYrri:
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case X86::VCMPPSYrri: {
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// Float comparison can be safely commuted for
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// Ordered/Unordered/Equal/NotEqual tests
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unsigned Imm = MI->getOperand(3).getImm() & 0x7;
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switch (Imm) {
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case 0x00: // EQUAL
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case 0x03: // UNORDERED
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case 0x04: // NOT EQUAL
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case 0x07: // ORDERED
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SrcOpIdx1 = 1;
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SrcOpIdx2 = 2;
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return true;
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}
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return false;
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}
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case X86::VFMADDPDr231r:
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case X86::VFMADDPSr231r:
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case X86::VFMADDSDr231r:
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@ -2488,6 +2488,7 @@ multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
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Operand CC, Intrinsic Int, string asm,
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string asm_alt, Domain d, ImmLeaf immLeaf,
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OpndItins itins = SSE_ALU_F32P> {
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let isCommutable = 1 in
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def rri : PIi8<0xC2, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
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[(set RC:$dst, (Int RC:$src1, RC:$src2, immLeaf:$cc))],
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340
test/CodeGen/X86/commute-fcmp.ll
Normal file
340
test/CodeGen/X86/commute-fcmp.ll
Normal file
@ -0,0 +1,340 @@
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; RUN: llc -O3 -mtriple=x86_64-unknown -mcpu=x86-64 -mattr=+sse2 < %s | FileCheck %s --check-prefix=SSE
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; RUN: llc -O3 -mtriple=x86_64-unknown -mcpu=x86-64 -mattr=+avx2 < %s | FileCheck %s --check-prefix=AVX
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;
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; Float Comparisons
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; Only equal/not-equal/ordered/unordered can be safely commuted
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;
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define <4 x i32> @commute_cmpps_eq(<4 x float>* %a0, <4 x float> %a1) #0 {
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;SSE-LABEL: commute_cmpps_eq
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;SSE: cmpeqps (%rdi), %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmpps_eq
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;AVX: vcmpeqps (%rdi), %xmm0, %xmm0
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;AVX-NEXT: retq
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%1 = load <4 x float>* %a0
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%2 = fcmp oeq <4 x float> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define <4 x i32> @commute_cmpps_ne(<4 x float>* %a0, <4 x float> %a1) #0 {
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;SSE-LABEL: commute_cmpps_ne
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;SSE: cmpneqps (%rdi), %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmpps_ne
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;AVX: vcmpneqps (%rdi), %xmm0, %xmm0
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;AVX-NEXT: retq
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%1 = load <4 x float>* %a0
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%2 = fcmp une <4 x float> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define <4 x i32> @commute_cmpps_ord(<4 x float>* %a0, <4 x float> %a1) #0 {
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;SSE-LABEL: commute_cmpps_ord
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;SSE: cmpordps (%rdi), %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmpps_ord
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;AVX: vcmpordps (%rdi), %xmm0, %xmm0
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;AVX-NEXT: retq
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%1 = load <4 x float>* %a0
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%2 = fcmp ord <4 x float> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define <4 x i32> @commute_cmpps_uno(<4 x float>* %a0, <4 x float> %a1) #0 {
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;SSE-LABEL: commute_cmpps_uno
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;SSE: cmpunordps (%rdi), %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmpps_uno
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;AVX: vcmpunordps (%rdi), %xmm0, %xmm0
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;AVX-NEXT: retq
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%1 = load <4 x float>* %a0
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%2 = fcmp uno <4 x float> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define <4 x i32> @commute_cmpps_lt(<4 x float>* %a0, <4 x float> %a1) #0 {
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;SSE-LABEL: commute_cmpps_lt
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;SSE: movaps (%rdi), %xmm1
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;SSE-NEXT: cmpltps %xmm0, %xmm1
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;SSE-NEXT: movaps %xmm1, %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmpps_lt
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;AVX: vmovaps (%rdi), %xmm1
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;AVX-NEXT: vcmpltps %xmm0, %xmm1, %xmm0
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;AVX-NEXT: retq
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%1 = load <4 x float>* %a0
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%2 = fcmp olt <4 x float> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define <4 x i32> @commute_cmpps_le(<4 x float>* %a0, <4 x float> %a1) #0 {
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;SSE-LABEL: commute_cmpps_le
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;SSE: movaps (%rdi), %xmm1
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;SSE-NEXT: cmpleps %xmm0, %xmm1
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;SSE-NEXT: movaps %xmm1, %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmpps_le
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;AVX: vmovaps (%rdi), %xmm1
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;AVX-NEXT: vcmpleps %xmm0, %xmm1, %xmm0
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;AVX-NEXT: retq
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%1 = load <4 x float>* %a0
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%2 = fcmp ole <4 x float> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define <8 x i32> @commute_cmpps_eq_ymm(<8 x float>* %a0, <8 x float> %a1) #0 {
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;AVX-LABEL: commute_cmpps_eq_ymm
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;AVX: vcmpeqps (%rdi), %ymm0, %ymm0
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;AVX-NEXT: retq
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%1 = load <8 x float>* %a0
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%2 = fcmp oeq <8 x float> %1, %a1
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%3 = sext <8 x i1> %2 to <8 x i32>
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ret <8 x i32> %3
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}
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define <8 x i32> @commute_cmpps_ne_ymm(<8 x float>* %a0, <8 x float> %a1) #0 {
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;AVX-LABEL: commute_cmpps_ne_ymm
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;AVX: vcmpneqps (%rdi), %ymm0, %ymm0
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;AVX-NEXT: retq
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%1 = load <8 x float>* %a0
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%2 = fcmp une <8 x float> %1, %a1
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%3 = sext <8 x i1> %2 to <8 x i32>
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ret <8 x i32> %3
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}
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define <8 x i32> @commute_cmpps_ord_ymm(<8 x float>* %a0, <8 x float> %a1) #0 {
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;AVX-LABEL: commute_cmpps_ord_ymm
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;AVX: vcmpordps (%rdi), %ymm0, %ymm0
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;AVX-NEXT: retq
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%1 = load <8 x float>* %a0
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%2 = fcmp ord <8 x float> %1, %a1
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%3 = sext <8 x i1> %2 to <8 x i32>
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ret <8 x i32> %3
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}
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define <8 x i32> @commute_cmpps_uno_ymm(<8 x float>* %a0, <8 x float> %a1) #0 {
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;AVX-LABEL: commute_cmpps_uno_ymm
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;AVX: vcmpunordps (%rdi), %ymm0, %ymm0
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;AVX-NEXT: retq
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%1 = load <8 x float>* %a0
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%2 = fcmp uno <8 x float> %1, %a1
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%3 = sext <8 x i1> %2 to <8 x i32>
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ret <8 x i32> %3
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}
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define <8 x i32> @commute_cmpps_lt_ymm(<8 x float>* %a0, <8 x float> %a1) #0 {
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;AVX-LABEL: commute_cmpps_lt_ymm
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;AVX: vmovaps (%rdi), %ymm1
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;AVX-NEXT: vcmpltps %ymm0, %ymm1, %ymm0
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;AVX-NEXT: retq
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%1 = load <8 x float>* %a0
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%2 = fcmp olt <8 x float> %1, %a1
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%3 = sext <8 x i1> %2 to <8 x i32>
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ret <8 x i32> %3
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}
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define <8 x i32> @commute_cmpps_le_ymm(<8 x float>* %a0, <8 x float> %a1) #0 {
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;AVX-LABEL: commute_cmpps_le_ymm
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;AVX: vmovaps (%rdi), %ymm1
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;AVX-NEXT: vcmpleps %ymm0, %ymm1, %ymm0
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;AVX-NEXT: retq
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%1 = load <8 x float>* %a0
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%2 = fcmp ole <8 x float> %1, %a1
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%3 = sext <8 x i1> %2 to <8 x i32>
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ret <8 x i32> %3
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}
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;
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; Double Comparisons
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; Only equal/not-equal/ordered/unordered can be safely commuted
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;
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define <2 x i64> @commute_cmppd_eq(<2 x double>* %a0, <2 x double> %a1) #0 {
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;SSE-LABEL: commute_cmppd_eq
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;SSE: cmpeqpd (%rdi), %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmppd_eq
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;AVX: vcmpeqpd (%rdi), %xmm0, %xmm0
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;AVX-NEXT: retq
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%1 = load <2 x double>* %a0
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%2 = fcmp oeq <2 x double> %1, %a1
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%3 = sext <2 x i1> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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define <2 x i64> @commute_cmppd_ne(<2 x double>* %a0, <2 x double> %a1) #0 {
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;SSE-LABEL: commute_cmppd_ne
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;SSE: cmpneqpd (%rdi), %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmppd_ne
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;AVX: vcmpneqpd (%rdi), %xmm0, %xmm0
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;AVX-NEXT: retq
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%1 = load <2 x double>* %a0
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%2 = fcmp une <2 x double> %1, %a1
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%3 = sext <2 x i1> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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define <2 x i64> @commute_cmppd_ord(<2 x double>* %a0, <2 x double> %a1) #0 {
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;SSE-LABEL: commute_cmppd_ord
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;SSE: cmpordpd (%rdi), %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmppd_ord
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;AVX: vcmpordpd (%rdi), %xmm0, %xmm0
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;AVX-NEXT: retq
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%1 = load <2 x double>* %a0
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%2 = fcmp ord <2 x double> %1, %a1
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%3 = sext <2 x i1> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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define <2 x i64> @commute_cmppd_uno(<2 x double>* %a0, <2 x double> %a1) #0 {
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;SSE-LABEL: commute_cmppd_uno
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;SSE: cmpunordpd (%rdi), %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmppd_uno
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;AVX: vcmpunordpd (%rdi), %xmm0, %xmm0
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;AVX-NEXT: retq
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%1 = load <2 x double>* %a0
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%2 = fcmp uno <2 x double> %1, %a1
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%3 = sext <2 x i1> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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define <2 x i64> @commute_cmppd_lt(<2 x double>* %a0, <2 x double> %a1) #0 {
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;SSE-LABEL: commute_cmppd_lt
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;SSE: movapd (%rdi), %xmm1
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;SSE-NEXT: cmpltpd %xmm0, %xmm1
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;SSE-NEXT: movapd %xmm1, %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmppd_lt
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;AVX: vmovapd (%rdi), %xmm1
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;AVX-NEXT: vcmpltpd %xmm0, %xmm1, %xmm0
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;AVX-NEXT: retq
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%1 = load <2 x double>* %a0
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%2 = fcmp olt <2 x double> %1, %a1
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%3 = sext <2 x i1> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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define <2 x i64> @commute_cmppd_le(<2 x double>* %a0, <2 x double> %a1) #0 {
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;SSE-LABEL: commute_cmppd_le
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;SSE: movapd (%rdi), %xmm1
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;SSE-NEXT: cmplepd %xmm0, %xmm1
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;SSE-NEXT: movapd %xmm1, %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmppd_le
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;AVX: vmovapd (%rdi), %xmm1
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;AVX-NEXT: vcmplepd %xmm0, %xmm1, %xmm0
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;AVX-NEXT: retq
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%1 = load <2 x double>* %a0
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%2 = fcmp ole <2 x double> %1, %a1
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%3 = sext <2 x i1> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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define <4 x i64> @commute_cmppd_eq_ymmm(<4 x double>* %a0, <4 x double> %a1) #0 {
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;AVX-LABEL: commute_cmppd_eq
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;AVX: vcmpeqpd (%rdi), %ymm0, %ymm0
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;AVX-NEXT: retq
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%1 = load <4 x double>* %a0
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%2 = fcmp oeq <4 x double> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i64>
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ret <4 x i64> %3
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}
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define <4 x i64> @commute_cmppd_ne_ymmm(<4 x double>* %a0, <4 x double> %a1) #0 {
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;AVX-LABEL: commute_cmppd_ne
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;AVX: vcmpneqpd (%rdi), %ymm0, %ymm0
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;AVX-NEXT: retq
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%1 = load <4 x double>* %a0
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%2 = fcmp une <4 x double> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i64>
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ret <4 x i64> %3
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}
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define <4 x i64> @commute_cmppd_ord_ymmm(<4 x double>* %a0, <4 x double> %a1) #0 {
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;AVX-LABEL: commute_cmppd_ord
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;AVX: vcmpordpd (%rdi), %ymm0, %ymm0
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;AVX-NEXT: retq
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%1 = load <4 x double>* %a0
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%2 = fcmp ord <4 x double> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i64>
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ret <4 x i64> %3
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}
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define <4 x i64> @commute_cmppd_uno_ymmm(<4 x double>* %a0, <4 x double> %a1) #0 {
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;AVX-LABEL: commute_cmppd_uno
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;AVX: vcmpunordpd (%rdi), %ymm0, %ymm0
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||||
;AVX-NEXT: retq
|
||||
|
||||
%1 = load <4 x double>* %a0
|
||||
%2 = fcmp uno <4 x double> %1, %a1
|
||||
%3 = sext <4 x i1> %2 to <4 x i64>
|
||||
ret <4 x i64> %3
|
||||
}
|
||||
|
||||
define <4 x i64> @commute_cmppd_lt_ymmm(<4 x double>* %a0, <4 x double> %a1) #0 {
|
||||
;AVX-LABEL: commute_cmppd_lt
|
||||
;AVX: vmovapd (%rdi), %ymm1
|
||||
;AVX-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0
|
||||
;AVX-NEXT: retq
|
||||
|
||||
%1 = load <4 x double>* %a0
|
||||
%2 = fcmp olt <4 x double> %1, %a1
|
||||
%3 = sext <4 x i1> %2 to <4 x i64>
|
||||
ret <4 x i64> %3
|
||||
}
|
||||
|
||||
define <4 x i64> @commute_cmppd_le_ymmm(<4 x double>* %a0, <4 x double> %a1) #0 {
|
||||
;AVX-LABEL: commute_cmppd_le
|
||||
;AVX: vmovapd (%rdi), %ymm1
|
||||
;AVX-NEXT: vcmplepd %ymm0, %ymm1, %ymm0
|
||||
;AVX-NEXT: retq
|
||||
|
||||
%1 = load <4 x double>* %a0
|
||||
%2 = fcmp ole <4 x double> %1, %a1
|
||||
%3 = sext <4 x i1> %2 to <4 x i64>
|
||||
ret <4 x i64> %3
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user