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Hide cpu name checking in ARMSubtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144154 91177308-0d34-0410-b5e6-96231b3b80d8
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lib/Target/ARM
@ -1080,7 +1080,7 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
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unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false);
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unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false);
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// ARM errata 602117: LDRD with base in list may result in incorrect base
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// ARM errata 602117: LDRD with base in list may result in incorrect base
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// register when interrupted or faulted.
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// register when interrupted or faulted.
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bool Errata602117 = EvenReg == BaseReg && STI->getCPUString() == "cortex-m3";
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bool Errata602117 = EvenReg == BaseReg && STI->isCortexM3();
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if (!Errata602117 &&
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if (!Errata602117 &&
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((EvenRegNum & 1) == 0 && (EvenRegNum + 1) == OddRegNum))
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((EvenRegNum & 1) == 0 && (EvenRegNum + 1) == OddRegNum))
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return false;
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return false;
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@ -191,6 +191,7 @@ protected:
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bool isCortexA8() const { return ARMProcFamily == CortexA8; }
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bool isCortexA8() const { return ARMProcFamily == CortexA8; }
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bool isCortexA9() const { return ARMProcFamily == CortexA9; }
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bool isCortexA9() const { return ARMProcFamily == CortexA9; }
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bool isCortexM3() const { return CPUString == "cortex-m3"; }
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bool hasARMOps() const { return !NoARM; }
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bool hasARMOps() const { return !NoARM; }
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