RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-11-30 23:20:54 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

AMDGPU/SI: Use v_readfirstlane_b32 when restoring SGPRs spilled to scratch

Browse Source 
We were using v_readlane_b32 with the lane set to zero, but this won't
work if thread 0 is not active.

Differential Revision: http://reviews.llvm.org/D19745

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268295 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2016-05-02 20:11:44 +00:00
parent 7614ec6431
commit 451c792dbc
2 changed files with 2 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lib/Target/AMDGPU/SIRegisterInfo.cpp
View File

@ -589,9 +589,8 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
.addImm(i * 4) // offset
.addMemOperand(MMO);
BuildMI(*MBB, MI, DL,
TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32), SubReg)
TII->get(AMDGPU::V_READFIRSTLANE_B32), SubReg)
.addReg(TmpReg, RegState::Kill)
.addImm(0)
.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
}
}

2
test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll
View File

@ -5,7 +5,7 @@
; Make sure we are handling hazards correctly.
; CHECK: buffer_load_dword [[VHI:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:12
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_readlane_b32 s[[HI:[0-9]+]], [[VHI]]
; CHECK-NEXT: v_readfirstlane_b32 s[[HI:[0-9]+]], [[VHI]]
; CHECK-NEXT: s_nop 4
; CHECK-NEXT: buffer_store_dword v0, off, s[0:[[HI]]{{\]}}, 0
; CHECK: s_endpgm