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Branches must be the last instruction in a Thumb2 IT block. Approved by Evan Cheng.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84212 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -107,8 +107,12 @@ bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
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// Finalize IT mask.
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ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
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unsigned Mask = 0, Pos = 3;
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while (MBBI != E && Pos) {
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// Branches, including tricky ones like LDM_RET, need to end an IT
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// block so check the instruction we just put in the block.
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while (MBBI != E && Pos &&
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(!MI->getDesc().isBranch() && !MI->getDesc().isReturn())) {
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MachineInstr *NMI = &*MBBI;
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MI = NMI;
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DebugLoc ndl = NMI->getDebugLoc();
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unsigned NPredReg = 0;
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ARMCC::CondCodes NCC = getPredicate(NMI, NPredReg);
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44
test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll
Normal file
44
test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll
Normal file
@ -0,0 +1,44 @@
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; RUN: llc < %s -mtriple=thumbv7-eabi -mcpu=cortex-a8 -float-abi=hard | FileCheck %s
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; A fix for PR5204 will require this check to be changed.
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%"struct.__gnu_cxx::__normal_iterator<char*,std::basic_string<char, std::char_traits<char>, std::allocator<char> > >" = type { i8* }
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%"struct.__gnu_cxx::new_allocator<char>" = type <{ i8 }>
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%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >" = type { %"struct.__gnu_cxx::__normal_iterator<char*,std::basic_string<char, std::char_traits<char>, std::allocator<char> > >" }
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%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >::_Rep" = type { %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >::_Rep_base" }
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%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >::_Rep_base" = type { i32, i32, i32 }
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define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this, %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) {
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; CHECK: _ZNKSs7compareERKSs:
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; CHECK: it ne
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; CHECK-NEXT: ldmfdne.w
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; CHECK-NEXT: itt eq
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; CHECK-NEXT: subeq.w
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; CHECK-NEXT: ldmfdeq.w
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entry:
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%0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i32> [#uses=3]
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%1 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) ; <i32> [#uses=3]
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%2 = icmp ult i32 %1, %0 ; <i1> [#uses=1]
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%3 = select i1 %2, i32 %1, i32 %0 ; <i32> [#uses=1]
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%4 = tail call arm_aapcs_vfpcc i8* @_ZNKSs7_M_dataEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i8*> [#uses=1]
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%5 = tail call arm_aapcs_vfpcc i8* @_ZNKSs4dataEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) ; <i8*> [#uses=1]
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%6 = tail call arm_aapcs_vfpcc i32 @memcmp(i8* %4, i8* %5, i32 %3) nounwind readonly ; <i32> [#uses=2]
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%7 = icmp eq i32 %6, 0 ; <i1> [#uses=1]
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br i1 %7, label %bb, label %bb1
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bb: ; preds = %entry
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%8 = sub i32 %0, %1 ; <i32> [#uses=1]
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ret i32 %8
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bb1: ; preds = %entry
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ret i32 %6
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}
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declare arm_aapcs_vfpcc i32 @memcmp(i8* nocapture, i8* nocapture, i32) nounwind readonly
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declare arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this)
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declare arm_aapcs_vfpcc i8* @_ZNKSs7_M_dataEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this)
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declare arm_aapcs_vfpcc i8* @_ZNKSs4dataEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this)
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