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[X86] Rename PABSB/D/W instructions to be consistent with SSE/AVX instructions instead of ending 128/256. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279927 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
3ed393863d
commit
460412aab8
@ -518,9 +518,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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{ X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
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{ X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
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{ X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
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{ X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
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{ X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
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{ X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
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{ X86::PABSBrr, X86::PABSBrm, TB_ALIGN_16 },
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{ X86::PABSDrr, X86::PABSDrm, TB_ALIGN_16 },
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{ X86::PABSWrr, X86::PABSWrm, TB_ALIGN_16 },
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{ X86::PCMPESTRIrr, X86::PCMPESTRIrm, TB_ALIGN_16 },
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{ X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 },
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{ X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 },
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@ -623,9 +623,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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{ X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
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{ X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
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{ X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
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{ X86::VPABSBrr128, X86::VPABSBrm128, 0 },
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{ X86::VPABSDrr128, X86::VPABSDrm128, 0 },
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{ X86::VPABSWrr128, X86::VPABSWrm128, 0 },
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{ X86::VPABSBrr, X86::VPABSBrm, 0 },
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{ X86::VPABSDrr, X86::VPABSDrm, 0 },
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{ X86::VPABSWrr, X86::VPABSWrm, 0 },
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{ X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 },
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{ X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
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{ X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
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@ -699,9 +699,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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{ X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
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{ X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
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{ X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
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{ X86::VPABSBrr256, X86::VPABSBrm256, 0 },
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{ X86::VPABSDrr256, X86::VPABSDrm256, 0 },
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{ X86::VPABSWrr256, X86::VPABSWrm256, 0 },
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{ X86::VPABSBYrr, X86::VPABSBYrm, 0 },
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{ X86::VPABSDYrr, X86::VPABSDYrm, 0 },
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{ X86::VPABSWYrr, X86::VPABSWYrm, 0 },
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{ X86::VPBROADCASTBrr, X86::VPBROADCASTBrm, 0 },
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{ X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm, 0 },
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{ X86::VPBROADCASTDrr, X86::VPBROADCASTDrm, 0 },
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@ -5392,35 +5392,35 @@ let Constraints = "$src1 = $dst" in {
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/// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
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multiclass SS3I_unop_rm<bits<8> opc, string OpcodeStr, ValueType vt,
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SDNode OpNode, PatFrag ld_frag> {
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def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (vt (OpNode VR128:$src)))],
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IIC_SSE_PABS_RR>, Sched<[WriteVecALU]>;
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def rr : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (vt (OpNode VR128:$src)))],
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IIC_SSE_PABS_RR>, Sched<[WriteVecALU]>;
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def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins i128mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst,
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(vt (OpNode (bitconvert (ld_frag addr:$src)))))],
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IIC_SSE_PABS_RM>, Sched<[WriteVecALULd]>;
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def rm : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins i128mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst,
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(vt (OpNode (bitconvert (ld_frag addr:$src)))))],
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IIC_SSE_PABS_RM>, Sched<[WriteVecALULd]>;
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}
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/// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
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multiclass SS3I_unop_rm_y<bits<8> opc, string OpcodeStr, ValueType vt,
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SDNode OpNode> {
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def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (vt (OpNode VR256:$src)))]>,
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Sched<[WriteVecALU]>;
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def Yrr : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (vt (OpNode VR256:$src)))]>,
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Sched<[WriteVecALU]>;
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def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
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(ins i256mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst,
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(vt (OpNode (bitconvert (loadv4i64 addr:$src)))))]>,
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Sched<[WriteVecALULd]>;
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def Yrm : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
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(ins i256mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst,
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(vt (OpNode (bitconvert (loadv4i64 addr:$src)))))]>,
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Sched<[WriteVecALULd]>;
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}
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// Helper fragments to match sext vXi1 to vXiY.
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@ -5445,15 +5445,15 @@ let Predicates = [HasAVX] in {
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def : Pat<(xor
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(bc_v2i64 (v16i1sextv16i8)),
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(bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
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(VPABSBrr128 VR128:$src)>;
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(VPABSBrr VR128:$src)>;
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def : Pat<(xor
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(bc_v2i64 (v8i1sextv8i16)),
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(bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
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(VPABSWrr128 VR128:$src)>;
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(VPABSWrr VR128:$src)>;
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def : Pat<(xor
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(bc_v2i64 (v4i1sextv4i32)),
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(bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
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(VPABSDrr128 VR128:$src)>;
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(VPABSDrr VR128:$src)>;
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}
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let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in {
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@ -5468,15 +5468,15 @@ let Predicates = [HasAVX2] in {
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def : Pat<(xor
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(bc_v4i64 (v32i1sextv32i8)),
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(bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
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(VPABSBrr256 VR256:$src)>;
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(VPABSBYrr VR256:$src)>;
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def : Pat<(xor
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(bc_v4i64 (v16i1sextv16i16)),
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(bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
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(VPABSWrr256 VR256:$src)>;
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(VPABSWYrr VR256:$src)>;
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def : Pat<(xor
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(bc_v4i64 (v8i1sextv8i32)),
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(bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
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(VPABSDrr256 VR256:$src)>;
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(VPABSDYrr VR256:$src)>;
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}
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defm PABSB : SS3I_unop_rm<0x1C, "pabsb", v16i8, X86Abs, memopv2i64>;
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@ -5487,15 +5487,15 @@ let Predicates = [UseSSSE3] in {
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def : Pat<(xor
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(bc_v2i64 (v16i1sextv16i8)),
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(bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
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(PABSBrr128 VR128:$src)>;
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(PABSBrr VR128:$src)>;
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def : Pat<(xor
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(bc_v2i64 (v8i1sextv8i16)),
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(bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
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(PABSWrr128 VR128:$src)>;
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(PABSWrr VR128:$src)>;
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def : Pat<(xor
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(bc_v2i64 (v4i1sextv4i32)),
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(bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
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(PABSDrr128 VR128:$src)>;
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(PABSDrr VR128:$src)>;
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}
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//===---------------------------------------------------------------------===//
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