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ARM: fix handling of SUB immediates in peephole opt.
We were negating an immediate that was going to be used in a SUBri form unnecessarily. Since ADD/SUB are very similar we *can* do that, but we have to change the SUB to an ADD at the same time. This also applies to ADD, and allows us to handle a slightly larger range of immediates for those two operations. rdar://25992245 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268276 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
2ab91e26c5
commit
464549ab4d
@ -2685,14 +2685,24 @@ bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
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Commute = UseMI->getOperand(2).getReg() != Reg;
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switch (UseOpc) {
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default: break;
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case ARM::SUBrr: {
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if (Commute)
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return false;
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ImmVal = -ImmVal;
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NewUseOpc = ARM::SUBri;
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// Fallthrough
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}
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case ARM::ADDrr:
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case ARM::SUBrr: {
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if (UseOpc == ARM::SUBrr && Commute)
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return false;
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// ADD/SUB are special because they're essentially the same operation, so
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// we can handle a larger range of immediates.
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if (ARM_AM::isSOImmTwoPartVal(ImmVal))
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NewUseOpc = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri;
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else if (ARM_AM::isSOImmTwoPartVal(-ImmVal)) {
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ImmVal = -ImmVal;
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NewUseOpc = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri;
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} else
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return false;
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SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
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SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
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break;
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}
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case ARM::ORRrr:
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case ARM::EORrr: {
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if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
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@ -2701,20 +2711,29 @@ bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
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SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
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switch (UseOpc) {
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default: break;
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case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
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case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
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case ARM::EORrr: NewUseOpc = ARM::EORri; break;
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}
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break;
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}
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case ARM::t2SUBrr: {
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if (Commute)
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return false;
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ImmVal = -ImmVal;
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NewUseOpc = ARM::t2SUBri;
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// Fallthrough
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}
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case ARM::t2ADDrr:
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case ARM::t2SUBrr: {
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if (UseOpc == ARM::t2SUBrr && Commute)
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return false;
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// ADD/SUB are special because they're essentially the same operation, so
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// we can handle a larger range of immediates.
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if (ARM_AM::isT2SOImmTwoPartVal(ImmVal))
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NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2ADDri : ARM::t2SUBri;
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else if (ARM_AM::isT2SOImmTwoPartVal(-ImmVal)) {
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ImmVal = -ImmVal;
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NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2SUBri : ARM::t2ADDri;
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} else
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return false;
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SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
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SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
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break;
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}
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case ARM::t2ORRrr:
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case ARM::t2EORrr: {
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if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
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@ -2723,7 +2742,6 @@ bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
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SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
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switch (UseOpc) {
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default: break;
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case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
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case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
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case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
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}
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60
test/CodeGen/MIR/ARM/imm-peephole-arm.mir
Normal file
60
test/CodeGen/MIR/ARM/imm-peephole-arm.mir
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@ -0,0 +1,60 @@
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# RUN: llc -run-pass=peephole-opts %s -o /dev/null 2>&1 | FileCheck %s
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# CHECK: [[IN:%.*]] = COPY %r0
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# CHECK: [[SUM1TMP:%.*]] = ADDri [[IN]], 133
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# CHECK: [[SUM1:%.*]] = ADDri killed [[SUM1TMP]], 25600
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# CHECK: [[SUM2TMP:%.*]] = SUBri [[IN]], 133
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# CHECK: [[SUM2:%.*]] = SUBri killed [[SUM2TMP]], 25600
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# CHECK: [[SUM3TMP:%.*]] = SUBri [[IN]], 133
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# CHECK: [[SUM3:%.*]] = SUBri killed [[SUM3TMP]], 25600
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# CHECK: [[SUM4TMP:%.*]] = ADDri killed [[IN]], 133
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# CHECK: [[SUM4:%.*]] = ADDri killed [[SUM4TMP]], 25600
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--- |
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target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
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target triple = "armv7-apple-ios"
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define i32 @foo(i32 %in) {
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ret i32 undef
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}
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...
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---
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name: foo
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registers:
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- { id: 0, class: gprnopc }
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- { id: 1, class: rgpr }
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- { id: 2, class: rgpr }
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- { id: 3, class: rgpr }
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- { id: 4, class: rgpr }
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- { id: 5, class: rgpr }
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- { id: 6, class: rgpr }
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- { id: 7, class: rgpr }
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- { id: 8, class: rgpr }
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liveins:
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- { reg: '%r0', virtual-reg: '%0' }
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body: |
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bb.0 (%ir-block.0):
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liveins: %r0
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%0 = COPY %r0
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%1 = MOVi32imm -25733
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%2 = SUBrr %0, killed %1, 14, _, _
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%3 = MOVi32imm 25733
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%4 = SUBrr %0, killed %3, 14, _, _
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%5 = MOVi32imm -25733
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%6 = ADDrr %0, killed %5, 14, _, _
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%7 = MOVi32imm 25733
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%8 = ADDrr killed %0, killed %7, 14, _, _
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%r0 = COPY killed %8
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BX_RET 14, _, implicit %r0
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...
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59
test/CodeGen/MIR/ARM/imm-peephole-thumb.mir
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59
test/CodeGen/MIR/ARM/imm-peephole-thumb.mir
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@ -0,0 +1,59 @@
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# RUN: llc -run-pass=peephole-opts %s -o /dev/null 2>&1 | FileCheck %s
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# CHECK: [[IN:%.*]] = COPY %r0
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# CHECK: [[SUM1TMP:%.*]] = t2ADDri [[IN]], 25600
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# CHECK: [[SUM1:%.*]] = t2ADDri killed [[SUM1TMP]], 133
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# CHECK: [[SUM2TMP:%.*]] = t2SUBri [[IN]], 25600
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# CHECK: [[SUM2:%.*]] = t2SUBri killed [[SUM2TMP]], 133
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# CHECK: [[SUM3TMP:%.*]] = t2SUBri [[IN]], 25600
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# CHECK: [[SUM3:%.*]] = t2SUBri killed [[SUM3TMP]], 133
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# CHECK: [[SUM4TMP:%.*]] = t2ADDri killed [[IN]], 25600
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# CHECK: [[SUM4:%.*]] = t2ADDri killed [[SUM4TMP]], 133
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--- |
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target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
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target triple = "thumbv7-apple-ios"
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define i32 @foo(i32 %in) {
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ret i32 undef
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}
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...
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---
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name: foo
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registers:
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- { id: 0, class: gprnopc }
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- { id: 1, class: rgpr }
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- { id: 2, class: rgpr }
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- { id: 3, class: rgpr }
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- { id: 4, class: rgpr }
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- { id: 5, class: rgpr }
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- { id: 6, class: rgpr }
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- { id: 7, class: rgpr }
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- { id: 8, class: rgpr }
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liveins:
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- { reg: '%r0', virtual-reg: '%0' }
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body: |
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bb.0 (%ir-block.0):
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liveins: %r0
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%0 = COPY %r0
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%1 = t2MOVi32imm -25733
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%2 = t2SUBrr %0, killed %1, 14, _, _
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%3 = t2MOVi32imm 25733
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%4 = t2SUBrr %0, killed %3, 14, _, _
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%5 = t2MOVi32imm -25733
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%6= t2ADDrr %0, killed %5, 14, _, _
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%7 = t2MOVi32imm 25733
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%8 = t2ADDrr killed %0, killed %7, 14, _, _
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%r0 = COPY killed %8
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tBX_RET 14, _, implicit %r0
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...
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