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[globalisel] OperandPredicateMatcher's shouldn't need to generate the MachineOperand expr. NFC

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Summary:
Each OperandPredicateMatcher shouldn't need to know how to generate the expression
to reference a MachineOperand. The OperandMatcher should provide it.

In addition to separating responsibilities, this also lays some groundwork for
decoupling source patterns from destination patterns to allow invented operands
or operands provided by GlobalISel's equivalent to the ComplexPattern<> class.

Depends on D29709

Reviewers: t.p.northover, ab, rovka, qcolombet, aditya_nandakumar

Reviewed By: ab

Subscribers: dberris, kristof.beyls, llvm-commits, igorb

Differential Revision: https://reviews.llvm.org/D29710

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295668 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2017-02-20 15:30:43 +00:00
parent 51a07570a2
commit 46f84bdef4
2 changed files with 22 additions and 21 deletions
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8
test/TableGen/GlobalISelEmitter.td
View File

@ -27,11 +27,11 @@ class I<dag OOps, dag IOps, list<dag> Pat>
//===- Test a simple pattern with regclass operands. ----------------------===//
// CHECK: if ((I.getOpcode() == TargetOpcode::G_ADD) &&
// CHECK-NEXT: (((MRI.getType(I.getOperand(0).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((/* Operand 0 */ (MRI.getType(I.getOperand(0).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: (((MRI.getType(I.getOperand(1).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((/* Operand 1 */ (MRI.getType(I.getOperand(1).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI))))) &&
// CHECK-NEXT: (((MRI.getType(I.getOperand(2).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((/* Operand 2 */ (MRI.getType(I.getOperand(2).getReg()) == (LLT::scalar(32))) &&
// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(I.getOperand(2).getReg(), MRI, TRI)))))) {
// CHECK-NEXT: // (add:i32 GPR32:i32:$src1, GPR32:i32:$src2) => (ADD:i32 GPR32:i32:$src1, GPR32:i32:$src2)
@ -46,7 +46,7 @@ def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2),
//===- Test a pattern with an MBB operand. --------------------------------===//
// CHECK: if ((I.getOpcode() == TargetOpcode::G_BR) &&
// CHECK-NEXT: (((I.getOperand(0).isMBB())))) {
// CHECK-NEXT: ((/* Operand 0 */ (I.getOperand(0).isMBB())))) {
// CHECK-NEXT: // (br (bb:Other):$target) => (BR (bb:Other):$target)
// CHECK-NEXT: I.setDesc(TII.get(MyTarget::BR));

35
utils/TableGen/GlobalISelEmitter.cpp
View File

@ -131,10 +131,9 @@ class OperandPredicateMatcher {
public:
virtual ~OperandPredicateMatcher() {}
/// Emit a C++ expression that checks the predicate for the OpIdx operand of
/// the instruction given in InsnVarName.
virtual void emitCxxPredicateExpr(raw_ostream &OS, StringRef InsnVarName,
unsigned OpIdx) const = 0;
/// Emit a C++ expression that checks the predicate for the given operand.
virtual void emitCxxPredicateExpr(raw_ostream &OS,
StringRef OperandExpr) const = 0;
};
/// Generates code to check that an operand is a particular LLT.
@ -145,10 +144,9 @@ protected:
public:
LLTOperandMatcher(std::string Ty) : Ty(Ty) {}
void emitCxxPredicateExpr(raw_ostream &OS, StringRef InsnVarName,
unsigned OpIdx) const override {
OS << "MRI.getType(" << InsnVarName << ".getOperand(" << OpIdx
<< ").getReg()) == (" << Ty << ")";
void emitCxxPredicateExpr(raw_ostream &OS,
StringRef OperandExpr) const override {
OS << "MRI.getType(" << OperandExpr << ".getReg()) == (" << Ty << ")";
}
};
@ -160,20 +158,20 @@ protected:
public:
RegisterBankOperandMatcher(const CodeGenRegisterClass &RC) : RC(RC) {}
void emitCxxPredicateExpr(raw_ostream &OS, StringRef InsnVarName,
unsigned OpIdx) const override {
void emitCxxPredicateExpr(raw_ostream &OS,
StringRef OperandExpr) const override {
OS << "(&RBI.getRegBankFromRegClass(" << RC.getQualifiedName()
<< "RegClass) == RBI.getRegBank(" << InsnVarName << ".getOperand("
<< OpIdx << ").getReg(), MRI, TRI))";
<< "RegClass) == RBI.getRegBank(" << OperandExpr
<< ".getReg(), MRI, TRI))";
}
};
/// Generates code to check that an operand is a basic block.
class MBBOperandMatcher : public OperandPredicateMatcher {
public:
void emitCxxPredicateExpr(raw_ostream &OS, StringRef InsnVarName,
unsigned OpIdx) const override {
OS << InsnVarName << ".getOperand(" << OpIdx << ").isMBB()";
void emitCxxPredicateExpr(raw_ostream &OS,
StringRef OperandExpr) const override {
OS << OperandExpr << ".isMBB()";
}
};
@ -185,12 +183,15 @@ protected:
public:
OperandMatcher(unsigned OpIdx) : OpIdx(OpIdx) {}
std::string getOperandExpr(StringRef InsnVarName) const {
return (InsnVarName + ".getOperand(" + std::to_string(OpIdx) + ")").str();
}
/// Emit a C++ expression that tests whether the instruction named in
/// InsnVarName matches all the predicate and all the operands.
void emitCxxPredicateExpr(raw_ostream &OS, StringRef InsnVarName) const {
OS << "(";
emitCxxPredicateListExpr(OS, InsnVarName, OpIdx);
OS << "(/* Operand " << OpIdx << " */ ";
emitCxxPredicateListExpr(OS, getOperandExpr(InsnVarName));
OS << ")";
}
};