From 46fe427fc74bb24e1649d65580febf7a22fa672b Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha <ahmed.bougacha@gmail.com>
Date: Tue, 2 Aug 2016 15:10:25 +0000
Subject: [PATCH] [GlobalISel] Add Legalized MachineFunction property.

Legalized: The MachineLegalizer ran; all pre-isel generic instructions
have been legalized, i.e., all instructions are now one of:
  - generic and always legal (e.g., COPY)
  - target-specific
  - legal pre-isel generic instructions.

This lets us enforce certain invariants across passes.
This property is GlobalISel-specific, but is always available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277470 91177308-0d34-0410-b5e6-96231b3b80d8
---
 include/llvm/CodeGen/MIRYamlMapping.h         |  3 ++
 include/llvm/CodeGen/MachineFunction.h        |  6 ++++
 lib/CodeGen/MIRParser/MIRParser.cpp           |  4 +++
 lib/CodeGen/MIRPrinter.cpp                    |  3 ++
 lib/CodeGen/MachineFunction.cpp               |  3 ++
 .../MIR/Generic/global-isel-properties.mir    | 34 +++++++++++++++++++
 6 files changed, 53 insertions(+)
 create mode 100644 test/CodeGen/MIR/Generic/global-isel-properties.mir

diff --git a/include/llvm/CodeGen/MIRYamlMapping.h b/include/llvm/CodeGen/MIRYamlMapping.h
index 7f9c4483333..1653e9a8ef4 100644
--- a/include/llvm/CodeGen/MIRYamlMapping.h
+++ b/include/llvm/CodeGen/MIRYamlMapping.h
@@ -384,6 +384,8 @@ struct MachineFunction {
   bool HasInlineAsm = false;
   // MachineFunctionProperties
   bool AllVRegsAllocated = false;
+  // GISel MachineFunctionProperties.
+  bool Legalized = false;
   // Register information
   bool IsSSA = false;
   bool TracksRegLiveness = false;
@@ -408,6 +410,7 @@ template <> struct MappingTraits<MachineFunction> {
     YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice);
     YamlIO.mapOptional("hasInlineAsm", MF.HasInlineAsm);
     YamlIO.mapOptional("allVRegsAllocated", MF.AllVRegsAllocated);
+    YamlIO.mapOptional("legalized", MF.Legalized);
     YamlIO.mapOptional("isSSA", MF.IsSSA);
     YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
     YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);
diff --git a/include/llvm/CodeGen/MachineFunction.h b/include/llvm/CodeGen/MachineFunction.h
index fadc05f1c08..5830af3416f 100644
--- a/include/llvm/CodeGen/MachineFunction.h
+++ b/include/llvm/CodeGen/MachineFunction.h
@@ -117,10 +117,16 @@ public:
   //  When this property is clear, liveness is no longer reliable.
   // AllVRegsAllocated: All virtual registers have been allocated; i.e. all
   //  register operands are physical registers.
+  // Legalized: In GlobalISel: the MachineLegalizer ran and all pre-isel generic
+  //  instructions have been legalized; i.e., all instructions are now one of:
+  //   - generic and always legal (e.g., COPY)
+  //   - target-specific
+  //   - legal pre-isel generic instructions.
   enum class Property : unsigned {
     IsSSA,
     TracksLiveness,
     AllVRegsAllocated,
+    Legalized,
     LastProperty,
   };
 
diff --git a/lib/CodeGen/MIRParser/MIRParser.cpp b/lib/CodeGen/MIRParser/MIRParser.cpp
index 4d8e4a90d1d..035b0ae5246 100644
--- a/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -292,6 +292,10 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
   MF.setHasInlineAsm(YamlMF.HasInlineAsm);
   if (YamlMF.AllVRegsAllocated)
     MF.getProperties().set(MachineFunctionProperties::Property::AllVRegsAllocated);
+
+  if (YamlMF.Legalized)
+    MF.getProperties().set(MachineFunctionProperties::Property::Legalized);
+
   PerFunctionMIParsingState PFS(MF, SM, IRSlots);
   if (initializeRegisterInfo(PFS, YamlMF))
     return true;
diff --git a/lib/CodeGen/MIRPrinter.cpp b/lib/CodeGen/MIRPrinter.cpp
index b42d45b5b5f..fdd7a42ac62 100644
--- a/lib/CodeGen/MIRPrinter.cpp
+++ b/lib/CodeGen/MIRPrinter.cpp
@@ -178,6 +178,9 @@ void MIRPrinter::print(const MachineFunction &MF) {
   YamlMF.AllVRegsAllocated = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::AllVRegsAllocated);
 
+  YamlMF.Legalized = MF.getProperties().hasProperty(
+      MachineFunctionProperties::Property::Legalized);
+
   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
   ModuleSlotTracker MST(MF.getFunction()->getParent());
   MST.incorporateFunction(*MF.getFunction());
diff --git a/lib/CodeGen/MachineFunction.cpp b/lib/CodeGen/MachineFunction.cpp
index a4c4ea4bb95..202cf3cdf03 100644
--- a/lib/CodeGen/MachineFunction.cpp
+++ b/lib/CodeGen/MachineFunction.cpp
@@ -76,6 +76,9 @@ void MachineFunctionProperties::print(raw_ostream &ROS, bool OnlySet) const {
       case Property::AllVRegsAllocated:
         ROS << (HasProperty ? "AllVRegsAllocated" : "HasVRegs");
         break;
+      case Property::Legalized:
+        ROS << (HasProperty ? "" : "not ") << "legalized";
+        break;
       default:
         break;
     }
diff --git a/test/CodeGen/MIR/Generic/global-isel-properties.mir b/test/CodeGen/MIR/Generic/global-isel-properties.mir
new file mode 100644
index 00000000000..44854153060
--- /dev/null
+++ b/test/CodeGen/MIR/Generic/global-isel-properties.mir
@@ -0,0 +1,34 @@
+# RUN: llc -run-pass none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses GlobalISel MachineFunction
+# properties correctly.
+# This doesn't require GlobalISel to be built, as the properties are always
+# available in CodeGen.
+
+--- |
+
+  define i32 @test_defaults() {
+  entry:
+    ret i32 0
+  }
+
+  define i32 @test() {
+  start:
+    ret i32 0
+  }
+
+...
+---
+# CHECK-LABEL: name: test_defaults
+# CHECK:      legalized: false
+name:            test_defaults
+body: |
+  bb.0:
+...
+---
+# CHECK-LABEL: name: test
+# CHECK:      legalized: true
+name: test
+legalized: true
+body: |
+  bb.0:
+...