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[Hexagon] Adding add/sub with saturation. Removing unused def. Cleaning up shift patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223680 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -170,6 +170,18 @@ def A2_combine_lh : T_ALU32_combineh<".l", ".h", 0b011, 0b110, 1>;
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def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>;
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def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>;
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}
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}
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class T_ALU32_3op_sfx<string mnemonic, string suffix, bits<3> MajOp,
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bits<3> MinOp, bit OpsRev, bit IsComm>
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: T_ALU32_3op<"", MajOp, MinOp, OpsRev, IsComm> {
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let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix;
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}
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let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123,
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isCodeGenOnly = 0 in {
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def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>;
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def A2_subsat : T_ALU32_3op_sfx<"sub", ":sat", 0b110, 0b110, 1, 0>;
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}
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multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
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multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
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bit OpsRev> {
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bit OpsRev> {
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def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;
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def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;
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@ -834,11 +846,10 @@ multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
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let isCodeGenOnly=0 in
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let isCodeGenOnly=0 in
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defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
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defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
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let hasSideEffects = 0 in
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def: Pat<(shl I32:$src1, (i32 16)), (A2_aslh I32:$src1)>;
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def COMBINE_ii : ALU32_ii<(outs DoubleRegs:$dst),
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def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>;
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(ins s8Imm:$src1, s8Imm:$src2),
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def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>;
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"$dst = combine(#$src1, #$src2)",
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def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>;
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[]>;
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// Mux.
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// Mux.
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def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
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def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
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@ -847,17 +858,6 @@ def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
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"$dst = vmux($src1, $src2, $src3)",
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"$dst = vmux($src1, $src2, $src3)",
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[]>;
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[]>;
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def : Pat <(shl (i32 IntRegs:$src1), (i32 16)),
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(A2_aslh IntRegs:$src1)>;
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def : Pat <(sra (i32 IntRegs:$src1), (i32 16)),
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(A2_asrh IntRegs:$src1)>;
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def : Pat <(sext_inreg (i32 IntRegs:$src1), i8),
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(A2_sxtb IntRegs:$src1)>;
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def : Pat <(sext_inreg (i32 IntRegs:$src1), i16),
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(A2_sxth IntRegs:$src1)>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// ALU32/PERM -
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// ALU32/PERM -
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@ -97,6 +97,12 @@ let Namespace = "Hexagon" in {
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def P2 : Rp<2, "p2">, DwarfRegNum<[65]>;
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def P2 : Rp<2, "p2">, DwarfRegNum<[65]>;
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def P3 : Rp<3, "p3">, DwarfRegNum<[66]>;
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def P3 : Rp<3, "p3">, DwarfRegNum<[66]>;
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// Fake register to represent USR.OVF bit. Artihmetic/saturating instruc-
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// tions modify this bit, and multiple such instructions are allowed in the
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// same packet. We need to ignore output dependencies on this bit, but not
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// on the entire USR.
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def USR_OVF : Rc<?, "usr.ovf">;
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// Control registers.
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// Control registers.
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def SA0 : Rc<0, "sa0">, DwarfRegNum<[67]>;
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def SA0 : Rc<0, "sa0">, DwarfRegNum<[67]>;
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def LC0 : Rc<1, "lc0">, DwarfRegNum<[68]>;
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def LC0 : Rc<1, "lc0">, DwarfRegNum<[68]>;
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@ -4,6 +4,8 @@
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# CHECK: r17 = add(r21, #31)
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# CHECK: r17 = add(r21, #31)
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0x11 0xdf 0x15 0xf3
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0x11 0xdf 0x15 0xf3
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# CHECK: r17 = add(r21, r31)
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# CHECK: r17 = add(r21, r31)
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0x11 0xdf 0x55 0xf6
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# CHECK: r17 = add(r21, r31):sat
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0x11 0xdf 0x15 0xf1
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0x11 0xdf 0x15 0xf1
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# CHECK: r17 = and(r21, r31)
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# CHECK: r17 = and(r21, r31)
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0xf1 0xc3 0x15 0x76
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0xf1 0xc3 0x15 0x76
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@ -20,6 +22,8 @@
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# CHECK: r17 = sub(#21, r31)
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# CHECK: r17 = sub(#21, r31)
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0x11 0xdf 0x35 0xf3
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0x11 0xdf 0x35 0xf3
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# CHECK: r17 = sub(r31, r21)
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# CHECK: r17 = sub(r31, r21)
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0x11 0xdf 0xd5 0xf6
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# CHECK: r17 = sub(r31, r21):sat
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0x11 0xc0 0xbf 0x70
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0x11 0xc0 0xbf 0x70
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# CHECK: r17 = sxtb(r31)
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# CHECK: r17 = sxtb(r31)
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0x15 0xc0 0x31 0x72
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0x15 0xc0 0x31 0x72
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