From 48be23cd65313b055ca80acb843ed244b18cd980 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Tue, 15 Jan 2008 22:02:54 +0000 Subject: [PATCH] rename SDTRet -> SDTNone. Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46017 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrInfo.td | 2 +- lib/Target/ARM/ARMInstrVFP.td | 2 +- lib/Target/Alpha/AlphaInstrInfo.td | 2 +- lib/Target/CellSPU/SPUNodes.td | 2 +- lib/Target/PowerPC/PPCInstrInfo.td | 6 +++--- lib/Target/TargetSelectionDAG.td | 6 ++++-- lib/Target/X86/X86InstrInfo.td | 4 ---- 7 files changed, 11 insertions(+), 13 deletions(-) diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 2709fc83509..1027b6c3d45 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -57,7 +57,7 @@ def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; -def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTRet, +def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInFlag]>; def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index ea87889c1c4..011819839ba 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -79,7 +79,7 @@ def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>; def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>; def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>; def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>; -def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTRet, [SDNPInFlag,SDNPOutFlag]>; +def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag,SDNPOutFlag]>; def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>; def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutFlag]>; def arm_fmdrr : SDNode<"ARMISD::FMDRR", SDT_FMDRR>; diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td index 5aaed81db21..474180f9154 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.td +++ b/lib/Target/Alpha/AlphaInstrInfo.td @@ -26,7 +26,7 @@ def Alpha_gprello : SDNode<"AlphaISD::GPRelLo", SDTIntBinOp, []>; def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi", SDTIntBinOp, []>; def Alpha_rellit : SDNode<"AlphaISD::RelLit", SDTIntBinOp, [SDNPMayLoad]>; -def retflag : SDNode<"AlphaISD::RET_FLAG", SDTRet, +def retflag : SDNode<"AlphaISD::RET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInFlag]>; // These are target-independent nodes, but have target-specific formats. diff --git a/lib/Target/CellSPU/SPUNodes.td b/lib/Target/CellSPU/SPUNodes.td index ae513d22663..b176fc98c7f 100644 --- a/lib/Target/CellSPU/SPUNodes.td +++ b/lib/Target/CellSPU/SPUNodes.td @@ -222,5 +222,5 @@ class NoEncode { // instruction scheduling doesn't disassociate them.) //===----------------------------------------------------------------------===// -def retflag : SDNode<"SPUISD::RET_FLAG", SDTRet, +def retflag : SDNode<"SPUISD::RET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInFlag]>; diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 495a1fd4224..616c0e7b4c8 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -105,13 +105,13 @@ def PPCcall_ELF : SDNode<"PPCISD::CALL_ELF", SDT_PPCCall, [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; -def PPCbctrl_Macho : SDNode<"PPCISD::BCTRL_Macho", SDTRet, +def PPCbctrl_Macho : SDNode<"PPCISD::BCTRL_Macho", SDTNone, [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; -def PPCbctrl_ELF : SDNode<"PPCISD::BCTRL_ELF", SDTRet, +def PPCbctrl_ELF : SDNode<"PPCISD::BCTRL_ELF", SDTNone, [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; -def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet, +def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInFlag]>; def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td index 091438a4abc..696f815d02a 100644 --- a/lib/Target/TargetSelectionDAG.td +++ b/lib/Target/TargetSelectionDAG.td @@ -154,7 +154,7 @@ def SDTBrind : SDTypeProfile<0, 1, [ // brind SDTCisPtrTy<0> ]>; -def SDTRet : SDTypeProfile<0, 0, []>; // ret +def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap def SDTLoad : SDTypeProfile<1, 1, [ // load SDTCisPtrTy<1> @@ -311,7 +311,9 @@ def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; -def ret : SDNode<"ISD::RET" , SDTRet, [SDNPHasChain]>; +def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>; +def trap : SDNode<"ISD::TRAP" , SDTNone, + [SDNPHasChain, SDNPSideEffect]>; // Do not use ld, st directly. Use load, extload, sextload, zextload, store, // and truncst (see below). diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 037fc2f16e1..de705de390d 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -107,10 +107,6 @@ def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, [SDNPHasChain, SDNPOptInFlag]>; -def SDT_TRAP : SDTypeProfile<0, 0, []>; -def trap : SDNode<"ISD::TRAP", SDT_TRAP, - [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>; - //===----------------------------------------------------------------------===// // X86 Operand Definitions. //