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misched: Handle "transient" non-instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165701 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -563,6 +563,8 @@ TargetInstrInfoImpl::getNumMicroOps(const InstrItineraryData *ItinData,
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/// Return the default expected latency for a def based on it's opcode.
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/// Return the default expected latency for a def based on it's opcode.
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unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel *SchedModel,
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unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel *SchedModel,
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const MachineInstr *DefMI) const {
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const MachineInstr *DefMI) const {
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if (DefMI->isTransient())
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return 0;
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if (DefMI->mayLoad())
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if (DefMI->mayLoad())
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return SchedModel->LoadLatency;
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return SchedModel->LoadLatency;
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if (isHighLatencyDef(DefMI->getOpcode()))
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if (isHighLatencyDef(DefMI->getOpcode()))
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@ -50,10 +50,12 @@ unsigned TargetSchedModel::getNumMicroOps(MachineInstr *MI) const {
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int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
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int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
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return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI);
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return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI);
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}
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}
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if (hasInstrSchedModel())
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if (hasInstrSchedModel()) {
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return resolveSchedClass(MI)->NumMicroOps;
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const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
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if (SCDesc->isValid())
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return 1;
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return SCDesc->NumMicroOps;
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}
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return MI->isTransient() ? 0 : 1;
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}
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}
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/// If we can determine the operand latency from the def only, without machine
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/// If we can determine the operand latency from the def only, without machine
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@ -199,7 +201,7 @@ unsigned TargetSchedModel::computeOperandLatency(
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report_fatal_error(ss.str());
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report_fatal_error(ss.str());
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}
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}
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#endif
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#endif
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return 1;
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return DefMI->isTransient() ? 0 : 1;
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}
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}
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unsigned TargetSchedModel::computeInstrLatency(const MachineInstr *MI) const {
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unsigned TargetSchedModel::computeInstrLatency(const MachineInstr *MI) const {
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@ -209,16 +211,18 @@ unsigned TargetSchedModel::computeInstrLatency(const MachineInstr *MI) const {
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return TII->getInstrLatency(&InstrItins, MI);
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return TII->getInstrLatency(&InstrItins, MI);
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if (hasInstrSchedModel()) {
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if (hasInstrSchedModel()) {
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unsigned Latency = 0;
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const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
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const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
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for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
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if (SCDesc->isValid()) {
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DefIdx != DefEnd; ++DefIdx) {
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unsigned Latency = 0;
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// Lookup the definition's write latency in SubtargetInfo.
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for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
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const MCWriteLatencyEntry *WLEntry =
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DefIdx != DefEnd; ++DefIdx) {
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STI->getWriteLatencyEntry(SCDesc, DefIdx);
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// Lookup the definition's write latency in SubtargetInfo.
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Latency = std::max(Latency, WLEntry->Cycles);
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const MCWriteLatencyEntry *WLEntry =
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STI->getWriteLatencyEntry(SCDesc, DefIdx);
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Latency = std::max(Latency, WLEntry->Cycles);
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}
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return Latency;
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}
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}
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return Latency;
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}
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}
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return TII->defaultDefLatency(&SchedModel, MI);
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return TII->defaultDefLatency(&SchedModel, MI);
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}
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}
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@ -251,10 +255,12 @@ computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
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// an unbuffered resource. If so, it treated like an in-order cpu.
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// an unbuffered resource. If so, it treated like an in-order cpu.
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if (hasInstrSchedModel()) {
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if (hasInstrSchedModel()) {
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const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
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const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
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for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
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if (SCDesc->isValid()) {
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*PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) {
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for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
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if (!SchedModel.getProcResource(PRI->ProcResourceIdx)->IsBuffered)
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*PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) {
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return 1;
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if (!SchedModel.getProcResource(PRI->ProcResourceIdx)->IsBuffered)
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return 1;
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}
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}
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}
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}
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}
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return 0;
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return 0;
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