From 490b1833a96bf0391ebdfba7828d43a8c3512851 Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Fri, 5 Dec 2008 05:30:02 +0000 Subject: [PATCH] Ignore IMPLICIT_DEF instructions when computing physreg liveness. While they appear to provide a normal clobbering def, they don't in the case of the awkward IMPLICIT_DEF+INSERT_SUBREG idiom. It would be good to change INSERT_SUBREG; until then, this change allows post-regalloc scheduling to cope in a mildly conservative way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60583 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/PostRASchedulerList.cpp | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp index ec56feaff96..b19525cbaa8 100644 --- a/lib/CodeGen/PostRASchedulerList.cpp +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -353,6 +353,13 @@ bool SchedulePostRATDList::BreakAntiDependencies() { I != E; ++I, --Count) { MachineInstr *MI = &*I; + // After regalloc, IMPLICIT_DEF instructions aren't safe to treat as + // dependence-breaking. In the case of an INSERT_SUBREG, the IMPLICIT_DEF + // is left behind appearing to clobber the super-register, while the + // subregister needs to remain live. So we just ignore them. + if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) + continue; + // Check if this instruction has an anti-dependence that we're // interested in. DenseMap::iterator C = CriticalAntiDeps.find(MI);