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Ignore IMPLICIT_DEF instructions when computing physreg liveness.

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While they appear to provide a normal clobbering def, they don't
in the case of the awkward IMPLICIT_DEF+INSERT_SUBREG idiom. It
would be good to change INSERT_SUBREG; until then, this change
allows post-regalloc scheduling to cope in a mildly conservative
way.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60583 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-12-05 05:30:02 +00:00
parent ae94e59416
commit 490b1833a9
1 changed files with 7 additions and 0 deletions
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7
lib/CodeGen/PostRASchedulerList.cpp
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@ -353,6 +353,13 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
I != E; ++I, --Count) {
MachineInstr *MI = &*I;
// After regalloc, IMPLICIT_DEF instructions aren't safe to treat as
// dependence-breaking. In the case of an INSERT_SUBREG, the IMPLICIT_DEF
// is left behind appearing to clobber the super-register, while the
// subregister needs to remain live. So we just ignore them.
if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
continue;
// Check if this instruction has an anti-dependence that we're
// interested in.
DenseMap<MachineInstr *, unsigned>::iterator C = CriticalAntiDeps.find(MI);