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[mips] Rename accumulator register classes and FP register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
7af40bfa66
commit
491d04969d
@ -112,7 +112,7 @@ class MipsAsmParser : public MCTargetAsmParser {
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parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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MipsAsmParser::OperandMatchResultTy
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parseACRegsDSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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parseACC64DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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bool searchSymbolAlias(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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unsigned RegKind);
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@ -223,7 +223,7 @@ public:
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Kind_AFGR64Regs,
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Kind_CCRRegs,
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Kind_FCCRegs,
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Kind_ACRegsDSP
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Kind_ACC64DSP
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};
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private:
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@ -405,8 +405,8 @@ public:
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return (Kind == k_Register) && Reg.Kind == Kind_FCCRegs;
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}
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bool isACRegsDSPAsm() const {
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return Kind == k_Register && Reg.Kind == Kind_ACRegsDSP;
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bool isACC64DSPAsm() const {
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return Kind == k_Register && Reg.Kind == Kind_ACC64DSP;
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}
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/// getStartLoc - Get the location of the first token of this operand.
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@ -1368,7 +1368,7 @@ MipsAsmParser::parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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}
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MipsAsmParser::OperandMatchResultTy
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MipsAsmParser::parseACRegsDSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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MipsAsmParser::parseACC64DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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// If the first token is not '$' we have an error.
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if (Parser.getTok().isNot(AsmToken::Dollar))
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return MatchOperand_NoMatch;
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@ -1390,10 +1390,10 @@ MipsAsmParser::parseACRegsDSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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if (NumString.getAsInteger(10, IntVal))
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return MatchOperand_NoMatch;
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unsigned Reg = matchRegisterByNumber(IntVal, Mips::ACRegsDSPRegClassID);
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unsigned Reg = matchRegisterByNumber(IntVal, Mips::ACC64DSPRegClassID);
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MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
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Op->setRegKind(MipsOperand::Kind_ACRegsDSP);
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Op->setRegKind(MipsOperand::Kind_ACC64DSP);
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Operands.push_back(Op);
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Parser.Lex(); // Eat the register number.
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@ -138,10 +138,10 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeACRegsDSPRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeHIRegsDSPRegisterClass(MCInst &Inst,
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unsigned RegNo,
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@ -477,14 +477,14 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeACRegsDSPRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo >= 4)
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return MCDisassembler::Fail;
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unsigned Reg = getReg(Decoder, Mips::ACRegsDSPRegClassID, RegNo);
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unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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@ -62,8 +62,8 @@ let usesCustomInserter = 1, Predicates = [HasStdEnc],
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/// Pseudo instructions for loading and storing accumulator registers.
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let isPseudo = 1, isCodeGenOnly = 1 in {
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defm LOAD_AC128 : LoadM<"", ACRegs128>;
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defm STORE_AC128 : StoreM<"", ACRegs128>;
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defm LOAD_ACC128 : LoadM<"", ACC128>;
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defm STORE_ACC128 : StoreM<"", ACC128>;
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}
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//===----------------------------------------------------------------------===//
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@ -191,15 +191,15 @@ def DMULT : Mult<"dmult", IIImult, GPR64Opnd, [HI64, LO64]>,
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MULT_FM<0, 0x1c>;
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def DMULTu : Mult<"dmultu", IIImult, GPR64Opnd, [HI64, LO64]>,
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MULT_FM<0, 0x1d>;
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def PseudoDMULT : MultDivPseudo<DMULT, ACRegs128, GPR64Opnd, MipsMult,
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def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
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IIImult>;
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def PseudoDMULTu : MultDivPseudo<DMULTu, ACRegs128, GPR64Opnd, MipsMultu,
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def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
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IIImult>;
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def DSDIV : Div<"ddiv", IIIdiv, GPR64Opnd, [HI64, LO64]>, MULT_FM<0, 0x1e>;
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def DUDIV : Div<"ddivu", IIIdiv, GPR64Opnd, [HI64, LO64]>, MULT_FM<0, 0x1f>;
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def PseudoDSDIV : MultDivPseudo<DSDIV, ACRegs128, GPR64Opnd, MipsDivRem,
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def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
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IIIdiv, 0, 1, 1>;
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def PseudoDUDIV : MultDivPseudo<DUDIV, ACRegs128, GPR64Opnd, MipsDivRemU,
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def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
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IIIdiv, 0, 1, 1>;
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let isCodeGenOnly = 1 in {
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@ -331,8 +331,8 @@ def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
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def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
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// mflo/hi patterns.
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def : MipsPat<(i64 (ExtractLOHI ACRegs128:$ac, imm:$lohi_idx)),
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(EXTRACT_SUBREG ACRegs128:$ac, imm:$lohi_idx)>;
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def : MipsPat<(i64 (ExtractLOHI ACC128:$ac, imm:$lohi_idx)),
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(EXTRACT_SUBREG ACC128:$ac, imm:$lohi_idx)>;
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//===----------------------------------------------------------------------===//
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// Instruction aliases
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@ -127,35 +127,35 @@ let Predicates = [HasStdEnc], isCodeGenOnly = 1 in {
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NoItinerary>, ADD_FM<0, 0xb>;
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}
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def MOVZ_I_S : CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32RegsOpnd, IIFmove>,
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def MOVZ_I_S : CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, IIFmove>,
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CMov_I_F_FM<18, 16>;
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let isCodeGenOnly = 1 in
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def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32RegsOpnd, IIFmove>,
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def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, IIFmove>,
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CMov_I_F_FM<18, 16>, Requires<[HasMips64, HasStdEnc]>;
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def MOVN_I_S : CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32RegsOpnd, IIFmove>,
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def MOVN_I_S : CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, IIFmove>,
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CMov_I_F_FM<19, 16>;
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let isCodeGenOnly = 1 in
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def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32RegsOpnd, IIFmove>,
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def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, IIFmove>,
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CMov_I_F_FM<19, 16>, Requires<[HasMips64, HasStdEnc]>;
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let Predicates = [NotFP64bit, HasStdEnc] in {
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def MOVZ_I_D32 : CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64RegsOpnd, IIFmove>,
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def MOVZ_I_D32 : CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, IIFmove>,
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CMov_I_F_FM<18, 17>;
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def MOVN_I_D32 : CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64RegsOpnd, IIFmove>,
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def MOVN_I_D32 : CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, IIFmove>,
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CMov_I_F_FM<19, 17>;
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}
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let Predicates = [IsFP64bit, HasStdEnc], isCodeGenOnly = 1 in {
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def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64RegsOpnd, IIFmove>,
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def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, IIFmove>,
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CMov_I_F_FM<18, 17>;
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def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64RegsOpnd,
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def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd,
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IIFmove>, CMov_I_F_FM<18, 17>;
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def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64RegsOpnd, IIFmove>,
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def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, IIFmove>,
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CMov_I_F_FM<19, 17>;
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def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64RegsOpnd,
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def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd,
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IIFmove>, CMov_I_F_FM<19, 17>;
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}
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@ -173,21 +173,21 @@ let isCodeGenOnly = 1 in
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def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, IIArith, MipsCMovFP_F>,
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CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]>;
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def MOVT_S : CMov_F_F_FT<"movt.s", FGR32RegsOpnd, IIFmove, MipsCMovFP_T>,
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def MOVT_S : CMov_F_F_FT<"movt.s", FGR32Opnd, IIFmove, MipsCMovFP_T>,
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CMov_F_F_FM<16, 1>;
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def MOVF_S : CMov_F_F_FT<"movf.s", FGR32RegsOpnd, IIFmove, MipsCMovFP_F>,
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def MOVF_S : CMov_F_F_FT<"movf.s", FGR32Opnd, IIFmove, MipsCMovFP_F>,
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CMov_F_F_FM<16, 0>;
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let Predicates = [NotFP64bit, HasStdEnc] in {
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def MOVT_D32 : CMov_F_F_FT<"movt.d", AFGR64RegsOpnd, IIFmove, MipsCMovFP_T>,
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def MOVT_D32 : CMov_F_F_FT<"movt.d", AFGR64Opnd, IIFmove, MipsCMovFP_T>,
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CMov_F_F_FM<17, 1>;
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def MOVF_D32 : CMov_F_F_FT<"movf.d", AFGR64RegsOpnd, IIFmove, MipsCMovFP_F>,
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def MOVF_D32 : CMov_F_F_FT<"movf.d", AFGR64Opnd, IIFmove, MipsCMovFP_F>,
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CMov_F_F_FM<17, 0>;
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}
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let Predicates = [IsFP64bit, HasStdEnc], isCodeGenOnly = 1 in {
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def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64RegsOpnd, IIFmove, MipsCMovFP_T>,
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def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, IIFmove, MipsCMovFP_T>,
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CMov_F_F_FM<17, 1>;
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def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64RegsOpnd, IIFmove, MipsCMovFP_F>,
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def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, IIFmove, MipsCMovFP_F>,
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CMov_F_F_FM<17, 0>;
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}
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@ -380,7 +380,7 @@ class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin> {
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dag OutOperandList = (outs GPR32:$rt);
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dag InOperandList = (ins ACRegsDSP:$ac, GPR32:$shift_rs);
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dag InOperandList = (ins ACC64DSP:$ac, GPR32:$shift_rs);
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string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
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InstrItinClass Itinerary = itin;
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}
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@ -388,35 +388,35 @@ class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin> {
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dag OutOperandList = (outs GPR32:$rt);
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dag InOperandList = (ins ACRegsDSP:$ac, uimm16:$shift_rs);
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dag InOperandList = (ins ACC64DSP:$ac, uimm16:$shift_rs);
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string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
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InstrItinClass Itinerary = itin;
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}
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class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
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dag OutOperandList = (outs ACRegsDSP:$ac);
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dag InOperandList = (ins simm16:$shift, ACRegsDSP:$acin);
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dag OutOperandList = (outs ACC64DSP:$ac);
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dag InOperandList = (ins simm16:$shift, ACC64DSP:$acin);
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string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
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list<dag> Pattern = [(set ACRegsDSP:$ac,
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(OpNode immSExt6:$shift, ACRegsDSP:$acin))];
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list<dag> Pattern = [(set ACC64DSP:$ac,
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(OpNode immSExt6:$shift, ACC64DSP:$acin))];
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string Constraints = "$acin = $ac";
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}
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class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
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dag OutOperandList = (outs ACRegsDSP:$ac);
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dag InOperandList = (ins GPR32:$rs, ACRegsDSP:$acin);
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dag OutOperandList = (outs ACC64DSP:$ac);
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dag InOperandList = (ins GPR32:$rs, ACC64DSP:$acin);
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string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
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list<dag> Pattern = [(set ACRegsDSP:$ac,
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(OpNode GPR32:$rs, ACRegsDSP:$acin))];
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list<dag> Pattern = [(set ACC64DSP:$ac,
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(OpNode GPR32:$rs, ACC64DSP:$acin))];
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string Constraints = "$acin = $ac";
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}
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class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
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dag OutOperandList = (outs ACRegsDSP:$ac);
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dag InOperandList = (ins GPR32:$rs, ACRegsDSP:$acin);
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dag OutOperandList = (outs ACC64DSP:$ac);
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dag InOperandList = (ins GPR32:$rs, ACC64DSP:$acin);
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string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
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list<dag> Pattern = [(set ACRegsDSP:$ac,
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(OpNode GPR32:$rs, ACRegsDSP:$acin))];
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list<dag> Pattern = [(set ACC64DSP:$ac,
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(OpNode GPR32:$rs, ACC64DSP:$acin))];
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string Constraints = "$acin = $ac";
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}
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@ -439,20 +439,20 @@ class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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}
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class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
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dag OutOperandList = (outs ACRegsDSP:$ac);
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dag InOperandList = (ins GPR32:$rs, GPR32:$rt, ACRegsDSP:$acin);
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dag OutOperandList = (outs ACC64DSP:$ac);
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dag InOperandList = (ins GPR32:$rs, GPR32:$rt, ACC64DSP:$acin);
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string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
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list<dag> Pattern = [(set ACRegsDSP:$ac,
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(OpNode GPR32:$rs, GPR32:$rt, ACRegsDSP:$acin))];
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list<dag> Pattern = [(set ACC64DSP:$ac,
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(OpNode GPR32:$rs, GPR32:$rt, ACC64DSP:$acin))];
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string Constraints = "$acin = $ac";
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}
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class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin> {
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dag OutOperandList = (outs ACRegsDSP:$ac);
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dag OutOperandList = (outs ACC64DSP:$ac);
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dag InOperandList = (ins GPR32:$rs, GPR32:$rt);
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string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
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list<dag> Pattern = [(set ACRegsDSP:$ac, (OpNode GPR32:$rs, GPR32:$rt))];
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list<dag> Pattern = [(set ACC64DSP:$ac, (OpNode GPR32:$rs, GPR32:$rt))];
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InstrItinClass Itinerary = itin;
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int AddedComplexity = 20;
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bit isCommutable = 1;
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@ -460,11 +460,11 @@ class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin> {
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dag OutOperandList = (outs ACRegsDSP:$ac);
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dag InOperandList = (ins GPR32:$rs, GPR32:$rt, ACRegsDSP:$acin);
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dag OutOperandList = (outs ACC64DSP:$ac);
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dag InOperandList = (ins GPR32:$rs, GPR32:$rt, ACC64DSP:$acin);
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string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
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list<dag> Pattern = [(set ACRegsDSP:$ac,
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(OpNode GPR32:$rs, GPR32:$rt, ACRegsDSP:$acin))];
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list<dag> Pattern = [(set ACC64DSP:$ac,
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(OpNode GPR32:$rs, GPR32:$rt, ACC64DSP:$acin))];
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InstrItinClass Itinerary = itin;
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int AddedComplexity = 20;
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string Constraints = "$acin = $ac";
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@ -1242,12 +1242,12 @@ def PREPEND : PREPEND_ENC, PREPEND_DESC;
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// Pseudos.
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let isPseudo = 1, isCodeGenOnly = 1 in {
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// Pseudo instructions for loading and storing accumulator registers.
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defm LOAD_AC_DSP : LoadM<"", ACRegsDSPOpnd>;
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defm STORE_AC_DSP : StoreM<"", ACRegsDSPOpnd>;
|
||||
defm LOAD_ACC64DSP : LoadM<"", ACC64DSPOpnd>;
|
||||
defm STORE_ACC64DSP : StoreM<"", ACC64DSPOpnd>;
|
||||
|
||||
// Pseudos for loading and storing ccond field of DSP control register.
|
||||
defm LOAD_CCOND_DSP : LoadM<"", DSPCC>;
|
||||
defm STORE_CCOND_DSP : StoreM<"", DSPCC>;
|
||||
defm LOAD_CCOND_DSP : LoadM<"load_ccond_dsp", DSPCC>;
|
||||
defm STORE_CCOND_DSP : StoreM<"store_ccond_dsp", DSPCC>;
|
||||
}
|
||||
|
||||
// Pseudo CMP and PICK instructions.
|
||||
@ -1384,12 +1384,12 @@ def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
|
||||
|
||||
// Extr patterns.
|
||||
class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
|
||||
DSPPat<(i32 (OpNode GPR32:$rs, ACRegsDSP:$ac)),
|
||||
(Instr ACRegsDSP:$ac, GPR32:$rs)>;
|
||||
DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
|
||||
(Instr ACC64DSP:$ac, GPR32:$rs)>;
|
||||
|
||||
class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
|
||||
DSPPat<(i32 (OpNode immZExt5:$shift, ACRegsDSP:$ac)),
|
||||
(Instr ACRegsDSP:$ac, immZExt5:$shift)>;
|
||||
DSPPat<(i32 (OpNode immZExt5:$shift, ACC64DSP:$ac)),
|
||||
(Instr ACC64DSP:$ac, immZExt5:$shift)>;
|
||||
|
||||
def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
|
||||
def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
|
||||
@ -1406,8 +1406,8 @@ def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
|
||||
|
||||
// mflo/hi patterns.
|
||||
let AddedComplexity = 20 in
|
||||
def : DSPPat<(i32 (ExtractLOHI ACRegsDSP:$ac, imm:$lohi_idx)),
|
||||
(EXTRACT_SUBREG ACRegsDSP:$ac, imm:$lohi_idx)>;
|
||||
def : DSPPat<(i32 (ExtractLOHI ACC64DSP:$ac, imm:$lohi_idx)),
|
||||
(EXTRACT_SUBREG ACC64DSP:$ac, imm:$lohi_idx)>;
|
||||
|
||||
// Indexed load patterns.
|
||||
class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :
|
||||
|
||||
@ -99,9 +99,9 @@ class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
|
||||
|
||||
multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
|
||||
SDPatternOperator OpNode = null_frag> {
|
||||
def _D32 : ADDS_FT<opstr, AFGR64RegsOpnd, Itin, IsComm, OpNode>,
|
||||
def _D32 : ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
|
||||
Requires<[NotFP64bit, HasStdEnc]>;
|
||||
def _D64 : ADDS_FT<opstr, FGR64RegsOpnd, Itin, IsComm, OpNode>,
|
||||
def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>,
|
||||
Requires<[IsFP64bit, HasStdEnc]> {
|
||||
string DecoderNamespace = "Mips64";
|
||||
}
|
||||
@ -115,18 +115,18 @@ class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
|
||||
|
||||
multiclass ABSS_M<string opstr, InstrItinClass Itin,
|
||||
SDPatternOperator OpNode= null_frag> {
|
||||
def _D32 : ABSS_FT<opstr, AFGR64RegsOpnd, AFGR64RegsOpnd, Itin, OpNode>,
|
||||
def _D32 : ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
|
||||
Requires<[NotFP64bit, HasStdEnc]>;
|
||||
def _D64 : ABSS_FT<opstr, FGR64RegsOpnd, FGR64RegsOpnd, Itin, OpNode>,
|
||||
def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
|
||||
Requires<[IsFP64bit, HasStdEnc]> {
|
||||
string DecoderNamespace = "Mips64";
|
||||
}
|
||||
}
|
||||
|
||||
multiclass ROUND_M<string opstr, InstrItinClass Itin> {
|
||||
def _D32 : ABSS_FT<opstr, FGR32RegsOpnd, AFGR64RegsOpnd, Itin>,
|
||||
def _D32 : ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>,
|
||||
Requires<[NotFP64bit, HasStdEnc]>;
|
||||
def _D64 : ABSS_FT<opstr, FGR32RegsOpnd, FGR64RegsOpnd, Itin>,
|
||||
def _D64 : ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>,
|
||||
Requires<[IsFP64bit, HasStdEnc]> {
|
||||
let DecoderNamespace = "Mips64";
|
||||
}
|
||||
@ -231,24 +231,24 @@ multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt> {
|
||||
def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC>, C_COND_FM<fmt, 15>;
|
||||
}
|
||||
|
||||
defm S : C_COND_M<"s", FGR32RegsOpnd, 16>;
|
||||
defm D32 : C_COND_M<"d", AFGR64RegsOpnd, 17>,
|
||||
defm S : C_COND_M<"s", FGR32Opnd, 16>;
|
||||
defm D32 : C_COND_M<"d", AFGR64Opnd, 17>,
|
||||
Requires<[NotFP64bit, HasStdEnc]>;
|
||||
let DecoderNamespace = "Mips64" in
|
||||
defm D64 : C_COND_M<"d", FGR64RegsOpnd, 17>, Requires<[IsFP64bit, HasStdEnc]>;
|
||||
defm D64 : C_COND_M<"d", FGR64Opnd, 17>, Requires<[IsFP64bit, HasStdEnc]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Floating Point Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
def ROUND_W_S : ABSS_FT<"round.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
|
||||
def ROUND_W_S : ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
|
||||
ABSS_FM<0xc, 16>;
|
||||
def TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
|
||||
def TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
|
||||
ABSS_FM<0xd, 16>;
|
||||
def CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
|
||||
def CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
|
||||
ABSS_FM<0xe, 16>;
|
||||
def FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
|
||||
def FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
|
||||
ABSS_FM<0xf, 16>;
|
||||
def CVT_W_S : ABSS_FT<"cvt.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
|
||||
def CVT_W_S : ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
|
||||
ABSS_FM<0x24, 16>;
|
||||
|
||||
defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>;
|
||||
@ -258,71 +258,71 @@ defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>;
|
||||
defm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>;
|
||||
|
||||
let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
|
||||
def ROUND_L_S : ABSS_FT<"round.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
|
||||
def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
|
||||
ABSS_FM<0x8, 16>;
|
||||
def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
|
||||
def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
|
||||
ABSS_FM<0x8, 17>;
|
||||
def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
|
||||
def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
|
||||
ABSS_FM<0x9, 16>;
|
||||
def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
|
||||
def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
|
||||
ABSS_FM<0x9, 17>;
|
||||
def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
|
||||
def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
|
||||
ABSS_FM<0xa, 16>;
|
||||
def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
|
||||
def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
|
||||
ABSS_FM<0xa, 17>;
|
||||
def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
|
||||
def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
|
||||
ABSS_FM<0xb, 16>;
|
||||
def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
|
||||
def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
|
||||
ABSS_FM<0xb, 17>;
|
||||
}
|
||||
|
||||
def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
|
||||
def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, IIFcvt>,
|
||||
ABSS_FM<0x20, 20>;
|
||||
def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
|
||||
def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
|
||||
ABSS_FM<0x25, 16>;
|
||||
def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
|
||||
def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
|
||||
ABSS_FM<0x25, 17>;
|
||||
|
||||
let Predicates = [NotFP64bit, HasStdEnc] in {
|
||||
def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32RegsOpnd, AFGR64RegsOpnd, IIFcvt>,
|
||||
def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, IIFcvt>,
|
||||
ABSS_FM<0x20, 17>;
|
||||
def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
|
||||
def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, IIFcvt>,
|
||||
ABSS_FM<0x21, 20>;
|
||||
def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
|
||||
def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, IIFcvt>,
|
||||
ABSS_FM<0x21, 16>;
|
||||
}
|
||||
|
||||
let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
|
||||
def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32RegsOpnd, FGR64RegsOpnd, IIFcvt>,
|
||||
def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, IIFcvt>,
|
||||
ABSS_FM<0x20, 17>;
|
||||
def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32RegsOpnd, FGR64RegsOpnd, IIFcvt>,
|
||||
def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, IIFcvt>,
|
||||
ABSS_FM<0x20, 21>;
|
||||
def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
|
||||
def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, IIFcvt>,
|
||||
ABSS_FM<0x21, 20>;
|
||||
def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
|
||||
def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
|
||||
ABSS_FM<0x21, 16>;
|
||||
def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
|
||||
def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, IIFcvt>,
|
||||
ABSS_FM<0x21, 21>;
|
||||
}
|
||||
|
||||
let isPseudo = 1, isCodeGenOnly = 1 in {
|
||||
def PseudoCVT_S_W : ABSS_FT<"", FGR32RegsOpnd, GPR32Opnd, IIFcvt>;
|
||||
def PseudoCVT_D32_W : ABSS_FT<"", AFGR64RegsOpnd, GPR32Opnd, IIFcvt>;
|
||||
def PseudoCVT_S_L : ABSS_FT<"", FGR64RegsOpnd, GPR64Opnd, IIFcvt>;
|
||||
def PseudoCVT_D64_W : ABSS_FT<"", FGR64RegsOpnd, GPR32Opnd, IIFcvt>;
|
||||
def PseudoCVT_D64_L : ABSS_FT<"", FGR64RegsOpnd, GPR64Opnd, IIFcvt>;
|
||||
def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, IIFcvt>;
|
||||
def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, IIFcvt>;
|
||||
def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, IIFcvt>;
|
||||
def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, IIFcvt>;
|
||||
def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, IIFcvt>;
|
||||
}
|
||||
|
||||
let Predicates = [NoNaNsFPMath, HasStdEnc] in {
|
||||
def FABS_S : ABSS_FT<"abs.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt, fabs>,
|
||||
def FABS_S : ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, IIFcvt, fabs>,
|
||||
ABSS_FM<0x5, 16>;
|
||||
def FNEG_S : ABSS_FT<"neg.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt, fneg>,
|
||||
def FNEG_S : ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, IIFcvt, fneg>,
|
||||
ABSS_FM<0x7, 16>;
|
||||
defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>;
|
||||
defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>;
|
||||
}
|
||||
|
||||
def FSQRT_S : ABSS_FT<"sqrt.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFsqrtSingle,
|
||||
def FSQRT_S : ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, IIFsqrtSingle,
|
||||
fsqrt>, ABSS_FM<0x4, 16>;
|
||||
defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
|
||||
|
||||
@ -334,164 +334,164 @@ defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
|
||||
/// Move Control Registers From/To CPU Registers
|
||||
def CFC1 : MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, IIFmove>, MFC1_FM<2>;
|
||||
def CTC1 : MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, IIFmove>, MFC1_FM<6>;
|
||||
def MFC1 : MFC1_FT<"mfc1", GPR32Opnd, FGR32RegsOpnd, IIFmoveC1, bitconvert>,
|
||||
def MFC1 : MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, IIFmoveC1, bitconvert>,
|
||||
MFC1_FM<0>;
|
||||
def MTC1 : MTC1_FT<"mtc1", FGR32RegsOpnd, GPR32Opnd, IIFmoveC1, bitconvert>,
|
||||
def MTC1 : MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, IIFmoveC1, bitconvert>,
|
||||
MFC1_FM<4>;
|
||||
def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64RegsOpnd, IIFmoveC1,
|
||||
def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, IIFmoveC1,
|
||||
bitconvert>, MFC1_FM<1>;
|
||||
def DMTC1 : MTC1_FT<"dmtc1", FGR64RegsOpnd, GPR64Opnd, IIFmoveC1,
|
||||
def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, IIFmoveC1,
|
||||
bitconvert>, MFC1_FM<5>;
|
||||
|
||||
def FMOV_S : ABSS_FT<"mov.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFmove>,
|
||||
def FMOV_S : ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, IIFmove>,
|
||||
ABSS_FM<0x6, 16>;
|
||||
def FMOV_D32 : ABSS_FT<"mov.d", AFGR64RegsOpnd, AFGR64RegsOpnd, IIFmove>,
|
||||
def FMOV_D32 : ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, IIFmove>,
|
||||
ABSS_FM<0x6, 17>, Requires<[NotFP64bit, HasStdEnc]>;
|
||||
def FMOV_D64 : ABSS_FT<"mov.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFmove>,
|
||||
def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, IIFmove>,
|
||||
ABSS_FM<0x6, 17>, Requires<[IsFP64bit, HasStdEnc]> {
|
||||
let DecoderNamespace = "Mips64";
|
||||
}
|
||||
|
||||
/// Floating Point Memory Instructions
|
||||
let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
|
||||
def LWC1_P8 : LW_FT<"lwc1", FGR32RegsOpnd, IIFLoad, mem64, load>,
|
||||
def LWC1_P8 : LW_FT<"lwc1", FGR32Opnd, IIFLoad, mem64, load>,
|
||||
LW_FM<0x31>;
|
||||
def SWC1_P8 : SW_FT<"swc1", FGR32RegsOpnd, IIFStore, mem64, store>,
|
||||
def SWC1_P8 : SW_FT<"swc1", FGR32Opnd, IIFStore, mem64, store>,
|
||||
LW_FM<0x39>;
|
||||
def LDC164_P8 : LW_FT<"ldc1", FGR64RegsOpnd, IIFLoad, mem64, load>,
|
||||
def LDC164_P8 : LW_FT<"ldc1", FGR64Opnd, IIFLoad, mem64, load>,
|
||||
LW_FM<0x35> {
|
||||
let isCodeGenOnly =1;
|
||||
}
|
||||
def SDC164_P8 : SW_FT<"sdc1", FGR64RegsOpnd, IIFStore, mem64, store>,
|
||||
def SDC164_P8 : SW_FT<"sdc1", FGR64Opnd, IIFStore, mem64, store>,
|
||||
LW_FM<0x3d> {
|
||||
let isCodeGenOnly =1;
|
||||
}
|
||||
}
|
||||
|
||||
let Predicates = [NotN64, HasStdEnc] in {
|
||||
def LWC1 : LW_FT<"lwc1", FGR32RegsOpnd, IIFLoad, mem, load>, LW_FM<0x31>;
|
||||
def SWC1 : SW_FT<"swc1", FGR32RegsOpnd, IIFStore, mem, store>, LW_FM<0x39>;
|
||||
def LWC1 : LW_FT<"lwc1", FGR32Opnd, IIFLoad, mem, load>, LW_FM<0x31>;
|
||||
def SWC1 : SW_FT<"swc1", FGR32Opnd, IIFStore, mem, store>, LW_FM<0x39>;
|
||||
}
|
||||
|
||||
let Predicates = [NotN64, HasMips64, HasStdEnc],
|
||||
DecoderNamespace = "Mips64" in {
|
||||
def LDC164 : LW_FT<"ldc1", FGR64RegsOpnd, IIFLoad, mem, load>, LW_FM<0x35>;
|
||||
def SDC164 : SW_FT<"sdc1", FGR64RegsOpnd, IIFStore, mem, store>, LW_FM<0x3d>;
|
||||
def LDC164 : LW_FT<"ldc1", FGR64Opnd, IIFLoad, mem, load>, LW_FM<0x35>;
|
||||
def SDC164 : SW_FT<"sdc1", FGR64Opnd, IIFStore, mem, store>, LW_FM<0x3d>;
|
||||
}
|
||||
|
||||
let Predicates = [NotN64, NotMips64, HasStdEnc] in {
|
||||
let isPseudo = 1, isCodeGenOnly = 1 in {
|
||||
def PseudoLDC1 : LW_FT<"", AFGR64RegsOpnd, IIFLoad, mem, load>;
|
||||
def PseudoSDC1 : SW_FT<"", AFGR64RegsOpnd, IIFStore, mem, store>;
|
||||
def PseudoLDC1 : LW_FT<"", AFGR64Opnd, IIFLoad, mem, load>;
|
||||
def PseudoSDC1 : SW_FT<"", AFGR64Opnd, IIFStore, mem, store>;
|
||||
}
|
||||
def LDC1 : LW_FT<"ldc1", AFGR64RegsOpnd, IIFLoad, mem>, LW_FM<0x35>;
|
||||
def SDC1 : SW_FT<"sdc1", AFGR64RegsOpnd, IIFStore, mem>, LW_FM<0x3d>;
|
||||
def LDC1 : LW_FT<"ldc1", AFGR64Opnd, IIFLoad, mem>, LW_FM<0x35>;
|
||||
def SDC1 : SW_FT<"sdc1", AFGR64Opnd, IIFStore, mem>, LW_FM<0x3d>;
|
||||
}
|
||||
|
||||
// Indexed loads and stores.
|
||||
let Predicates = [HasFPIdx, HasStdEnc] in {
|
||||
def LWXC1 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, GPR32Opnd, IIFLoad, load>,
|
||||
def LWXC1 : LWXC1_FT<"lwxc1", FGR32Opnd, GPR32Opnd, IIFLoad, load>,
|
||||
LWXC1_FM<0>;
|
||||
def SWXC1 : SWXC1_FT<"swxc1", FGR32RegsOpnd, GPR32Opnd, IIFStore, store>,
|
||||
def SWXC1 : SWXC1_FT<"swxc1", FGR32Opnd, GPR32Opnd, IIFStore, store>,
|
||||
SWXC1_FM<8>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in {
|
||||
def LDXC1 : LWXC1_FT<"ldxc1", AFGR64RegsOpnd, GPR32Opnd, IIFLoad, load>,
|
||||
def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, GPR32Opnd, IIFLoad, load>,
|
||||
LWXC1_FM<1>;
|
||||
def SDXC1 : SWXC1_FT<"sdxc1", AFGR64RegsOpnd, GPR32Opnd, IIFStore, store>,
|
||||
def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, GPR32Opnd, IIFStore, store>,
|
||||
SWXC1_FM<9>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in {
|
||||
def LDXC164 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, GPR32Opnd, IIFLoad, load>,
|
||||
def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, GPR32Opnd, IIFLoad, load>,
|
||||
LWXC1_FM<1>;
|
||||
def SDXC164 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, GPR32Opnd, IIFStore, store>,
|
||||
def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, GPR32Opnd, IIFStore, store>,
|
||||
SWXC1_FM<9>;
|
||||
}
|
||||
|
||||
// n64
|
||||
let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in {
|
||||
def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, GPR64Opnd, IIFLoad, load>,
|
||||
def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32Opnd, GPR64Opnd, IIFLoad, load>,
|
||||
LWXC1_FM<0>;
|
||||
def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, GPR64Opnd, IIFLoad,
|
||||
def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64Opnd, GPR64Opnd, IIFLoad,
|
||||
load>, LWXC1_FM<1>;
|
||||
def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32RegsOpnd, GPR64Opnd, IIFStore,
|
||||
def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32Opnd, GPR64Opnd, IIFStore,
|
||||
store>, SWXC1_FM<8>;
|
||||
def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, GPR64Opnd, IIFStore,
|
||||
def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64Opnd, GPR64Opnd, IIFStore,
|
||||
store>, SWXC1_FM<9>;
|
||||
}
|
||||
|
||||
// Load/store doubleword indexed unaligned.
|
||||
let Predicates = [NotMips64, HasStdEnc] in {
|
||||
def LUXC1 : LWXC1_FT<"luxc1", AFGR64RegsOpnd, GPR32Opnd, IIFLoad>,
|
||||
def LUXC1 : LWXC1_FT<"luxc1", AFGR64Opnd, GPR32Opnd, IIFLoad>,
|
||||
LWXC1_FM<0x5>;
|
||||
def SUXC1 : SWXC1_FT<"suxc1", AFGR64RegsOpnd, GPR32Opnd, IIFStore>,
|
||||
def SUXC1 : SWXC1_FT<"suxc1", AFGR64Opnd, GPR32Opnd, IIFStore>,
|
||||
SWXC1_FM<0xd>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMips64, HasStdEnc],
|
||||
DecoderNamespace="Mips64" in {
|
||||
def LUXC164 : LWXC1_FT<"luxc1", FGR64RegsOpnd, GPR32Opnd, IIFLoad>,
|
||||
def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, GPR32Opnd, IIFLoad>,
|
||||
LWXC1_FM<0x5>;
|
||||
def SUXC164 : SWXC1_FT<"suxc1", FGR64RegsOpnd, GPR32Opnd, IIFStore>,
|
||||
def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, GPR32Opnd, IIFStore>,
|
||||
SWXC1_FM<0xd>;
|
||||
}
|
||||
|
||||
/// Floating-point Aritmetic
|
||||
def FADD_S : ADDS_FT<"add.s", FGR32RegsOpnd, IIFadd, 1, fadd>,
|
||||
def FADD_S : ADDS_FT<"add.s", FGR32Opnd, IIFadd, 1, fadd>,
|
||||
ADDS_FM<0x00, 16>;
|
||||
defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>;
|
||||
def FDIV_S : ADDS_FT<"div.s", FGR32RegsOpnd, IIFdivSingle, 0, fdiv>,
|
||||
def FDIV_S : ADDS_FT<"div.s", FGR32Opnd, IIFdivSingle, 0, fdiv>,
|
||||
ADDS_FM<0x03, 16>;
|
||||
defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>;
|
||||
def FMUL_S : ADDS_FT<"mul.s", FGR32RegsOpnd, IIFmulSingle, 1, fmul>,
|
||||
def FMUL_S : ADDS_FT<"mul.s", FGR32Opnd, IIFmulSingle, 1, fmul>,
|
||||
ADDS_FM<0x02, 16>;
|
||||
defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>;
|
||||
def FSUB_S : ADDS_FT<"sub.s", FGR32RegsOpnd, IIFadd, 0, fsub>,
|
||||
def FSUB_S : ADDS_FT<"sub.s", FGR32Opnd, IIFadd, 0, fsub>,
|
||||
ADDS_FM<0x01, 16>;
|
||||
defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>;
|
||||
|
||||
let Predicates = [HasMips32r2, HasStdEnc] in {
|
||||
def MADD_S : MADDS_FT<"madd.s", FGR32RegsOpnd, IIFmulSingle, fadd>,
|
||||
def MADD_S : MADDS_FT<"madd.s", FGR32Opnd, IIFmulSingle, fadd>,
|
||||
MADDS_FM<4, 0>;
|
||||
def MSUB_S : MADDS_FT<"msub.s", FGR32RegsOpnd, IIFmulSingle, fsub>,
|
||||
def MSUB_S : MADDS_FT<"msub.s", FGR32Opnd, IIFmulSingle, fsub>,
|
||||
MADDS_FM<5, 0>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in {
|
||||
def NMADD_S : NMADDS_FT<"nmadd.s", FGR32RegsOpnd, IIFmulSingle, fadd>,
|
||||
def NMADD_S : NMADDS_FT<"nmadd.s", FGR32Opnd, IIFmulSingle, fadd>,
|
||||
MADDS_FM<6, 0>;
|
||||
def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32RegsOpnd, IIFmulSingle, fsub>,
|
||||
def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32Opnd, IIFmulSingle, fsub>,
|
||||
MADDS_FM<7, 0>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in {
|
||||
def MADD_D32 : MADDS_FT<"madd.d", AFGR64RegsOpnd, IIFmulDouble, fadd>,
|
||||
def MADD_D32 : MADDS_FT<"madd.d", AFGR64Opnd, IIFmulDouble, fadd>,
|
||||
MADDS_FM<4, 1>;
|
||||
def MSUB_D32 : MADDS_FT<"msub.d", AFGR64RegsOpnd, IIFmulDouble, fsub>,
|
||||
def MSUB_D32 : MADDS_FT<"msub.d", AFGR64Opnd, IIFmulDouble, fsub>,
|
||||
MADDS_FM<5, 1>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in {
|
||||
def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64RegsOpnd, IIFmulDouble, fadd>,
|
||||
def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64Opnd, IIFmulDouble, fadd>,
|
||||
MADDS_FM<6, 1>;
|
||||
def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64RegsOpnd, IIFmulDouble, fsub>,
|
||||
def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64Opnd, IIFmulDouble, fsub>,
|
||||
MADDS_FM<7, 1>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in {
|
||||
def MADD_D64 : MADDS_FT<"madd.d", FGR64RegsOpnd, IIFmulDouble, fadd>,
|
||||
def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, IIFmulDouble, fadd>,
|
||||
MADDS_FM<4, 1>;
|
||||
def MSUB_D64 : MADDS_FT<"msub.d", FGR64RegsOpnd, IIFmulDouble, fsub>,
|
||||
def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, IIFmulDouble, fsub>,
|
||||
MADDS_FM<5, 1>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
|
||||
isCodeGenOnly=1 in {
|
||||
def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64RegsOpnd, IIFmulDouble, fadd>,
|
||||
def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, IIFmulDouble, fadd>,
|
||||
MADDS_FM<6, 1>;
|
||||
def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64RegsOpnd, IIFmulDouble, fsub>,
|
||||
def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, IIFmulDouble, fsub>,
|
||||
MADDS_FM<7, 1>;
|
||||
}
|
||||
|
||||
@ -543,9 +543,9 @@ def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
|
||||
// This pseudo instr gets expanded into 2 mtc1 instrs after register
|
||||
// allocation.
|
||||
def BuildPairF64 :
|
||||
PseudoSE<(outs AFGR64RegsOpnd:$dst),
|
||||
PseudoSE<(outs AFGR64Opnd:$dst),
|
||||
(ins GPR32Opnd:$lo, GPR32Opnd:$hi),
|
||||
[(set AFGR64RegsOpnd:$dst,
|
||||
[(set AFGR64Opnd:$dst,
|
||||
(MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>;
|
||||
|
||||
// This pseudo instr gets expanded into 2 mfc1 instrs after register
|
||||
@ -553,9 +553,9 @@ def BuildPairF64 :
|
||||
// if n is 0, lower part of src is extracted.
|
||||
// if n is 1, higher part of src is extracted.
|
||||
def ExtractElementF64 :
|
||||
PseudoSE<(outs GPR32Opnd:$dst), (ins AFGR64RegsOpnd:$src, i32imm:$n),
|
||||
PseudoSE<(outs GPR32Opnd:$dst), (ins AFGR64Opnd:$src, i32imm:$n),
|
||||
[(set GPR32Opnd:$dst,
|
||||
(MipsExtractElementF64 AFGR64RegsOpnd:$src, imm:$n))]>;
|
||||
(MipsExtractElementF64 AFGR64Opnd:$src, imm:$n))]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// InstAliases.
|
||||
@ -571,18 +571,18 @@ def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
|
||||
|
||||
def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)),
|
||||
(PseudoCVT_S_W GPR32Opnd:$src)>;
|
||||
def : MipsPat<(MipsTruncIntFP FGR32RegsOpnd:$src),
|
||||
(TRUNC_W_S FGR32RegsOpnd:$src)>;
|
||||
def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
|
||||
(TRUNC_W_S FGR32Opnd:$src)>;
|
||||
|
||||
let Predicates = [NotFP64bit, HasStdEnc] in {
|
||||
def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
|
||||
(PseudoCVT_D32_W GPR32Opnd:$src)>;
|
||||
def : MipsPat<(MipsTruncIntFP AFGR64RegsOpnd:$src),
|
||||
(TRUNC_W_D32 AFGR64RegsOpnd:$src)>;
|
||||
def : MipsPat<(f32 (fround AFGR64RegsOpnd:$src)),
|
||||
(CVT_S_D32 AFGR64RegsOpnd:$src)>;
|
||||
def : MipsPat<(f64 (fextend FGR32RegsOpnd:$src)),
|
||||
(CVT_D32_S FGR32RegsOpnd:$src)>;
|
||||
def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
|
||||
(TRUNC_W_D32 AFGR64Opnd:$src)>;
|
||||
def : MipsPat<(f32 (fround AFGR64Opnd:$src)),
|
||||
(CVT_S_D32 AFGR64Opnd:$src)>;
|
||||
def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
|
||||
(CVT_D32_S FGR32Opnd:$src)>;
|
||||
}
|
||||
|
||||
let Predicates = [IsFP64bit, HasStdEnc] in {
|
||||
@ -596,17 +596,17 @@ let Predicates = [IsFP64bit, HasStdEnc] in {
|
||||
def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)),
|
||||
(PseudoCVT_D64_L GPR64Opnd:$src)>;
|
||||
|
||||
def : MipsPat<(MipsTruncIntFP FGR64RegsOpnd:$src),
|
||||
(TRUNC_W_D64 FGR64RegsOpnd:$src)>;
|
||||
def : MipsPat<(MipsTruncIntFP FGR32RegsOpnd:$src),
|
||||
(TRUNC_L_S FGR32RegsOpnd:$src)>;
|
||||
def : MipsPat<(MipsTruncIntFP FGR64RegsOpnd:$src),
|
||||
(TRUNC_L_D64 FGR64RegsOpnd:$src)>;
|
||||
def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
|
||||
(TRUNC_W_D64 FGR64Opnd:$src)>;
|
||||
def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
|
||||
(TRUNC_L_S FGR32Opnd:$src)>;
|
||||
def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
|
||||
(TRUNC_L_D64 FGR64Opnd:$src)>;
|
||||
|
||||
def : MipsPat<(f32 (fround FGR64RegsOpnd:$src)),
|
||||
(CVT_S_D64 FGR64RegsOpnd:$src)>;
|
||||
def : MipsPat<(f64 (fextend FGR32RegsOpnd:$src)),
|
||||
(CVT_D64_S FGR32RegsOpnd:$src)>;
|
||||
def : MipsPat<(f32 (fround FGR64Opnd:$src)),
|
||||
(CVT_S_D64 FGR64Opnd:$src)>;
|
||||
def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
|
||||
(CVT_D64_S FGR32Opnd:$src)>;
|
||||
}
|
||||
|
||||
// Patterns for loads/stores with a reg+imm operand.
|
||||
|
||||
@ -698,10 +698,10 @@ class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
|
||||
// Pseudo multiply add/sub instruction with explicit accumulator register
|
||||
// operands.
|
||||
class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
|
||||
: PseudoSE<(outs ACRegs:$ac),
|
||||
(ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACRegs:$acin),
|
||||
[(set ACRegs:$ac,
|
||||
(OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACRegs:$acin))],
|
||||
: PseudoSE<(outs ACC64:$ac),
|
||||
(ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
|
||||
[(set ACC64:$ac,
|
||||
(OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
|
||||
IIImult>,
|
||||
PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
|
||||
string Constraints = "$acin = $ac";
|
||||
@ -875,8 +875,8 @@ let usesCustomInserter = 1 in {
|
||||
|
||||
/// Pseudo instructions for loading and storing accumulator registers.
|
||||
let isPseudo = 1, isCodeGenOnly = 1 in {
|
||||
defm LOAD_AC64 : LoadM<"", ACRegs>;
|
||||
defm STORE_AC64 : StoreM<"", ACRegs>;
|
||||
defm LOAD_ACC64 : LoadM<"", ACC64>;
|
||||
defm STORE_ACC64 : StoreM<"", ACC64>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -1033,13 +1033,13 @@ def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI, LO]>,
|
||||
MULT_FM<0, 0x18>;
|
||||
def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI, LO]>,
|
||||
MULT_FM<0, 0x19>;
|
||||
def PseudoMULT : MultDivPseudo<MULT, ACRegs, GPR32Opnd, MipsMult, IIImult>;
|
||||
def PseudoMULTu : MultDivPseudo<MULTu, ACRegs, GPR32Opnd, MipsMultu, IIImult>;
|
||||
def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>;
|
||||
def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>;
|
||||
def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI, LO]>, MULT_FM<0, 0x1a>;
|
||||
def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI, LO]>, MULT_FM<0, 0x1b>;
|
||||
def PseudoSDIV : MultDivPseudo<SDIV, ACRegs, GPR32Opnd, MipsDivRem, IIIdiv,
|
||||
def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv,
|
||||
0, 1, 1>;
|
||||
def PseudoUDIV : MultDivPseudo<UDIV, ACRegs, GPR32Opnd, MipsDivRemU, IIIdiv,
|
||||
def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv,
|
||||
0, 1, 1>;
|
||||
|
||||
def MTHI : MoveToLOHI<"mthi", GPR32Opnd, [HI]>, MTLO_FM<0x11>;
|
||||
@ -1370,8 +1370,8 @@ defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
|
||||
def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
|
||||
|
||||
// mflo/hi patterns.
|
||||
def : MipsPat<(i32 (ExtractLOHI ACRegs:$ac, imm:$lohi_idx)),
|
||||
(EXTRACT_SUBREG ACRegs:$ac, imm:$lohi_idx)>;
|
||||
def : MipsPat<(i32 (ExtractLOHI ACC64:$ac, imm:$lohi_idx)),
|
||||
(EXTRACT_SUBREG ACC64:$ac, imm:$lohi_idx)>;
|
||||
|
||||
// Load halfword/word patterns.
|
||||
let AddedComplexity = 40 in {
|
||||
|
||||
@ -64,7 +64,7 @@ class AFPR64<bits<16> Enc, string n, list<Register> subregs>
|
||||
}
|
||||
|
||||
// Accumulator Registers
|
||||
class ACC<bits<16> Enc, string n, list<Register> subregs>
|
||||
class ACCReg<bits<16> Enc, string n, list<Register> subregs>
|
||||
: MipsRegWithSubRegs<Enc, n, subregs> {
|
||||
let SubRegIndices = [sub_lo, sub_hi];
|
||||
let CoveredBySubRegs = 1;
|
||||
@ -192,12 +192,12 @@ let Namespace = "Mips" in {
|
||||
def HWR29 : MipsReg<29, "29">;
|
||||
|
||||
// Accum registers
|
||||
def AC0 : ACC<0, "ac0", [LO, HI]>;
|
||||
def AC1 : ACC<1, "ac1", [LO1, HI1]>;
|
||||
def AC2 : ACC<2, "ac2", [LO2, HI2]>;
|
||||
def AC3 : ACC<3, "ac3", [LO3, HI3]>;
|
||||
def AC0 : ACCReg<0, "ac0", [LO, HI]>;
|
||||
def AC1 : ACCReg<1, "ac1", [LO1, HI1]>;
|
||||
def AC2 : ACCReg<2, "ac2", [LO2, HI2]>;
|
||||
def AC3 : ACCReg<3, "ac3", [LO3, HI3]>;
|
||||
|
||||
def AC0_64 : ACC<0, "ac0", [LO64, HI64]>;
|
||||
def AC0_64 : ACCReg<0, "ac0", [LO64, HI64]>;
|
||||
|
||||
// DSP-ASE control register fields.
|
||||
def DSPPos : Register<"">;
|
||||
@ -314,15 +314,15 @@ def HIRegs64 : RegisterClass<"Mips", [i64], 64, (add HI64)>;
|
||||
def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable;
|
||||
|
||||
// Accumulator Registers
|
||||
def ACRegs : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
|
||||
def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
|
||||
let Size = 64;
|
||||
}
|
||||
|
||||
def ACRegs128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> {
|
||||
def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> {
|
||||
let Size = 128;
|
||||
}
|
||||
|
||||
def ACRegsDSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
|
||||
def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
|
||||
let Size = 64;
|
||||
}
|
||||
|
||||
@ -343,9 +343,9 @@ def GPR64AsmOperand : MipsAsmRegOperand {
|
||||
let ParserMethod = "parseGPR64";
|
||||
}
|
||||
|
||||
def ACRegsDSPAsmOperand : MipsAsmRegOperand {
|
||||
let Name = "ACRegsDSPAsm";
|
||||
let ParserMethod = "parseACRegsDSP";
|
||||
def ACC64DSPAsmOperand : MipsAsmRegOperand {
|
||||
let Name = "ACC64DSPAsm";
|
||||
let ParserMethod = "parseACC64DSP";
|
||||
}
|
||||
|
||||
def CCRAsmOperand : MipsAsmRegOperand {
|
||||
@ -394,15 +394,15 @@ def HWRegsOpnd : RegisterOperand<HWRegs> {
|
||||
let ParserMatchClass = HWRegsAsmOperand;
|
||||
}
|
||||
|
||||
def AFGR64RegsOpnd : RegisterOperand<AFGR64> {
|
||||
def AFGR64Opnd : RegisterOperand<AFGR64> {
|
||||
let ParserMatchClass = AFGR64AsmOperand;
|
||||
}
|
||||
|
||||
def FGR64RegsOpnd : RegisterOperand<FGR64> {
|
||||
def FGR64Opnd : RegisterOperand<FGR64> {
|
||||
let ParserMatchClass = FGR64AsmOperand;
|
||||
}
|
||||
|
||||
def FGR32RegsOpnd : RegisterOperand<FGR32> {
|
||||
def FGR32Opnd : RegisterOperand<FGR32> {
|
||||
let ParserMatchClass = FGR32AsmOperand;
|
||||
}
|
||||
|
||||
@ -410,6 +410,6 @@ def FCCRegsOpnd : RegisterOperand<FCC> {
|
||||
let ParserMatchClass = FCCRegsAsmOperand;
|
||||
}
|
||||
|
||||
def ACRegsDSPOpnd : RegisterOperand<ACRegsDSP> {
|
||||
let ParserMatchClass = ACRegsDSPAsmOperand;
|
||||
def ACC64DSPOpnd : RegisterOperand<ACC64DSP> {
|
||||
let ParserMatchClass = ACC64DSPAsmOperand;
|
||||
}
|
||||
|
||||
@ -77,24 +77,24 @@ bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
|
||||
case Mips::STORE_CCOND_DSP_P8:
|
||||
expandStoreCCond(MBB, I);
|
||||
break;
|
||||
case Mips::LOAD_AC64:
|
||||
case Mips::LOAD_AC64_P8:
|
||||
case Mips::LOAD_AC_DSP:
|
||||
case Mips::LOAD_AC_DSP_P8:
|
||||
case Mips::LOAD_ACC64:
|
||||
case Mips::LOAD_ACC64_P8:
|
||||
case Mips::LOAD_ACC64DSP:
|
||||
case Mips::LOAD_ACC64DSP_P8:
|
||||
expandLoadACC(MBB, I, 4);
|
||||
break;
|
||||
case Mips::LOAD_AC128:
|
||||
case Mips::LOAD_AC128_P8:
|
||||
case Mips::LOAD_ACC128:
|
||||
case Mips::LOAD_ACC128_P8:
|
||||
expandLoadACC(MBB, I, 8);
|
||||
break;
|
||||
case Mips::STORE_AC64:
|
||||
case Mips::STORE_AC64_P8:
|
||||
case Mips::STORE_AC_DSP:
|
||||
case Mips::STORE_AC_DSP_P8:
|
||||
case Mips::STORE_ACC64:
|
||||
case Mips::STORE_ACC64_P8:
|
||||
case Mips::STORE_ACC64DSP:
|
||||
case Mips::STORE_ACC64DSP_P8:
|
||||
expandStoreACC(MBB, I, 4);
|
||||
break;
|
||||
case Mips::STORE_AC128:
|
||||
case Mips::STORE_AC128_P8:
|
||||
case Mips::STORE_ACC128:
|
||||
case Mips::STORE_ACC128_P8:
|
||||
expandStoreACC(MBB, I, 8);
|
||||
break;
|
||||
case TargetOpcode::COPY:
|
||||
@ -210,10 +210,10 @@ void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,
|
||||
bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) {
|
||||
unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
|
||||
|
||||
if (Mips::ACRegsDSPRegClass.contains(Dst, Src))
|
||||
if (Mips::ACC64DSPRegClass.contains(Dst, Src))
|
||||
return expandCopyACC(MBB, I, Dst, Src, 4);
|
||||
|
||||
if (Mips::ACRegs128RegClass.contains(Dst, Src))
|
||||
if (Mips::ACC128RegClass.contains(Dst, Src))
|
||||
return expandCopyACC(MBB, I, Dst, Src, 8);
|
||||
|
||||
return false;
|
||||
|
||||
@ -425,8 +425,8 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
|
||||
}
|
||||
|
||||
case MipsISD::InsertLOHI: {
|
||||
unsigned RCID = Subtarget.hasDSP() ? Mips::ACRegsDSPRegClassID :
|
||||
Mips::ACRegsRegClassID;
|
||||
unsigned RCID = Subtarget.hasDSP() ? Mips::ACC64DSPRegClassID :
|
||||
Mips::ACC64RegClassID;
|
||||
SDValue RegClass = CurDAG->getTargetConstant(RCID, MVT::i32);
|
||||
SDValue LoIdx = CurDAG->getTargetConstant(Mips::sub_lo, MVT::i32);
|
||||
SDValue HiIdx = CurDAG->getTargetConstant(Mips::sub_hi, MVT::i32);
|
||||
|
||||
@ -38,8 +38,8 @@ namespace llvm {
|
||||
|
||||
virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
|
||||
if (VT == MVT::Untyped)
|
||||
return Subtarget->hasDSP() ? &Mips::ACRegsDSPRegClass :
|
||||
&Mips::ACRegsRegClass;
|
||||
return Subtarget->hasDSP() ? &Mips::ACC64DSPRegClass :
|
||||
&Mips::ACC64RegClass;
|
||||
|
||||
return TargetLowering::getRepRegClassFor(VT);
|
||||
}
|
||||
|
||||
@ -189,12 +189,12 @@ storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
Opc = IsN64 ? Mips::SW_P8 : Mips::SW;
|
||||
else if (Mips::GPR64RegClass.hasSubClassEq(RC))
|
||||
Opc = IsN64 ? Mips::SD_P8 : Mips::SD;
|
||||
else if (Mips::ACRegsRegClass.hasSubClassEq(RC))
|
||||
Opc = IsN64 ? Mips::STORE_AC64_P8 : Mips::STORE_AC64;
|
||||
else if (Mips::ACRegsDSPRegClass.hasSubClassEq(RC))
|
||||
Opc = IsN64 ? Mips::STORE_AC_DSP_P8 : Mips::STORE_AC_DSP;
|
||||
else if (Mips::ACRegs128RegClass.hasSubClassEq(RC))
|
||||
Opc = IsN64 ? Mips::STORE_AC128_P8 : Mips::STORE_AC128;
|
||||
else if (Mips::ACC64RegClass.hasSubClassEq(RC))
|
||||
Opc = IsN64 ? Mips::STORE_ACC64_P8 : Mips::STORE_ACC64;
|
||||
else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
|
||||
Opc = IsN64 ? Mips::STORE_ACC64DSP_P8 : Mips::STORE_ACC64DSP;
|
||||
else if (Mips::ACC128RegClass.hasSubClassEq(RC))
|
||||
Opc = IsN64 ? Mips::STORE_ACC128_P8 : Mips::STORE_ACC128;
|
||||
else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
|
||||
Opc = IsN64 ? Mips::STORE_CCOND_DSP_P8 : Mips::STORE_CCOND_DSP;
|
||||
else if (Mips::FGR32RegClass.hasSubClassEq(RC))
|
||||
@ -222,12 +222,12 @@ loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
|
||||
else if (Mips::GPR64RegClass.hasSubClassEq(RC))
|
||||
Opc = IsN64 ? Mips::LD_P8 : Mips::LD;
|
||||
else if (Mips::ACRegsRegClass.hasSubClassEq(RC))
|
||||
Opc = IsN64 ? Mips::LOAD_AC64_P8 : Mips::LOAD_AC64;
|
||||
else if (Mips::ACRegsDSPRegClass.hasSubClassEq(RC))
|
||||
Opc = IsN64 ? Mips::LOAD_AC_DSP_P8 : Mips::LOAD_AC_DSP;
|
||||
else if (Mips::ACRegs128RegClass.hasSubClassEq(RC))
|
||||
Opc = IsN64 ? Mips::LOAD_AC128_P8 : Mips::LOAD_AC128;
|
||||
else if (Mips::ACC64RegClass.hasSubClassEq(RC))
|
||||
Opc = IsN64 ? Mips::LOAD_ACC64_P8 : Mips::LOAD_ACC64;
|
||||
else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
|
||||
Opc = IsN64 ? Mips::LOAD_ACC64DSP_P8 : Mips::LOAD_ACC64DSP;
|
||||
else if (Mips::ACC128RegClass.hasSubClassEq(RC))
|
||||
Opc = IsN64 ? Mips::LOAD_ACC128_P8 : Mips::LOAD_ACC128;
|
||||
else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
|
||||
Opc = IsN64 ? Mips::LOAD_CCOND_DSP_P8 : Mips::LOAD_CCOND_DSP;
|
||||
else if (Mips::FGR32RegClass.hasSubClassEq(RC))
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user