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[Hexagon] Deleting a lot of old variants of intrinsics and updating references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227338 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
b616a18f02
commit
4925c39604
@ -172,6 +172,16 @@ inline SDValue XformUToUM1Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
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}
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// XformSToSM2Imm - Return a target constant decremented by 2.
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inline SDValue XformSToSM2Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm - 2, MVT::i32);
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}
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// XformSToSM3Imm - Return a target constant decremented by 3.
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inline SDValue XformSToSM3Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm - 3, MVT::i32);
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}
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// Include the pieces autogenerated from the target description.
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#include "HexagonGenDAGISel.inc"
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@ -39,6 +39,20 @@ def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
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return XformSToSM1Imm(imm);
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}]>;
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// SDNode for converting immediate C to C-2.
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def DEC2_CONST_SIGNED : SDNodeXForm<imm, [{
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// Return the byte immediate const-2 as an SDNode.
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int32_t imm = N->getSExtValue();
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return XformSToSM2Imm(imm);
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}]>;
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// SDNode for converting immediate C to C-3.
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def DEC3_CONST_SIGNED : SDNodeXForm<imm, [{
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// Return the byte immediate const-3 as an SDNode.
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int32_t imm = N->getSExtValue();
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return XformSToSM3Imm(imm);
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}]>;
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// SDNode for converting immediate C to C-1.
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def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
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// Return the byte immediate const-1 as an SDNode.
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@ -638,6 +638,9 @@ def: T_RR_pat<C2_bitsclr, int_hexagon_C2_bitsclr>;
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def: T_RI_pat<C2_bitsclri, int_hexagon_C2_bitsclri>;
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def: T_RR_pat<C2_bitsset, int_hexagon_C2_bitsset>;
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// Linear feedback-shift Iteration.
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def : T_PP_pat <S2_lfsp, int_hexagon_S2_lfsp>;
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// Shift by immediate and add
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def : T_RRI_pat<S2_addasl_rrri, int_hexagon_S2_addasl_rrri>;
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@ -706,6 +709,22 @@ def : T_RR_pat <S2_lsl_r_r, int_hexagon_S2_lsl_r_r>;
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def : T_RR_pat <S2_asr_r_r_sat, int_hexagon_S2_asr_r_r_sat>;
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def : T_RR_pat <S2_asl_r_r_sat, int_hexagon_S2_asl_r_r_sat>;
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def : T_R_pat <A2_sxtw, int_hexagon_A2_sxtw>;
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def : T_R_pat <S2_brev, int_hexagon_S2_brev>;
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def : T_R_pat <A2_abs, int_hexagon_A2_abs>;
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def : T_R_pat <A2_abssat, int_hexagon_A2_abssat>;
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def : T_R_pat <A2_negsat, int_hexagon_A2_negsat>;
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def : T_R_pat <A2_swiz, int_hexagon_A2_swiz>;
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def : T_P_pat <A2_sat, int_hexagon_A2_sat>;
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def : T_R_pat <A2_sath, int_hexagon_A2_sath>;
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def : T_R_pat <A2_satuh, int_hexagon_A2_satuh>;
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def : T_R_pat <A2_satub, int_hexagon_A2_satub>;
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def : T_R_pat <A2_satb, int_hexagon_A2_satb>;
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def : T_RI_pat <S2_asr_i_r, int_hexagon_S2_asr_i_r>;
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def : T_RI_pat <S2_lsr_i_r, int_hexagon_S2_lsr_i_r>;
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def : T_RI_pat <S2_asl_i_r, int_hexagon_S2_asl_i_r>;
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@ -716,6 +735,33 @@ def : T_RI_pat <S2_asr_i_r_rnd_goodsyntax,
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// Shift left by immediate with saturation.
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def : T_RI_pat <S2_asl_i_r_sat, int_hexagon_S2_asl_i_r_sat>;
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//===----------------------------------------------------------------------===//
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// Template 'def pat' to map tableidx[bhwd] intrinsics to :raw instructions.
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//===----------------------------------------------------------------------===//
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class S2op_tableidx_pat <Intrinsic IntID, InstHexagon OutputInst,
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SDNodeXForm XformImm>
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: Pat <(IntID IntRegs:$src1, IntRegs:$src2, u4ImmPred:$src3, u5ImmPred:$src4),
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(OutputInst IntRegs:$src1, IntRegs:$src2, u4ImmPred:$src3,
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(XformImm u5ImmPred:$src4))>;
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// Table Index : Extract and insert bits.
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// Map to the real hardware instructions after subtracting appropriate
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// values from the 4th input operand. Please note that subtraction is not
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// needed for int_hexagon_S2_tableidxb_goodsyntax.
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def : Pat <(int_hexagon_S2_tableidxb_goodsyntax IntRegs:$src1, IntRegs:$src2,
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u4ImmPred:$src3, u5ImmPred:$src4),
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(S2_tableidxb IntRegs:$src1, IntRegs:$src2,
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u4ImmPred:$src3, u5ImmPred:$src4)>;
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def : S2op_tableidx_pat <int_hexagon_S2_tableidxh_goodsyntax, S2_tableidxh,
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DEC_CONST_SIGNED>;
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def : S2op_tableidx_pat <int_hexagon_S2_tableidxw_goodsyntax, S2_tableidxw,
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DEC2_CONST_SIGNED>;
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def : S2op_tableidx_pat <int_hexagon_S2_tableidxd_goodsyntax, S2_tableidxd,
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DEC3_CONST_SIGNED>;
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//
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// ALU 32 types.
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//
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@ -2561,42 +2607,10 @@ class di_LDInstPI_diu4<string opc, Intrinsic IntID>
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* ALU32/PERM *
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*********************************************************************/
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// ALU32 / PERM / Combine.
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def HEXAGON_A2_combinew:
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di_ALU32_sisi <"combine", int_hexagon_A2_combinew>;
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def HEXAGON_A2_combine_hh:
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si_MInst_sisi_hh <"combine", int_hexagon_A2_combine_hh>;
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def HEXAGON_A2_combine_lh:
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si_MInst_sisi_lh <"combine", int_hexagon_A2_combine_lh>;
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def HEXAGON_A2_combine_hl:
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si_MInst_sisi_hl <"combine", int_hexagon_A2_combine_hl>;
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def HEXAGON_A2_combine_ll:
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si_MInst_sisi_ll <"combine", int_hexagon_A2_combine_ll>;
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def HEXAGON_A2_combineii:
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di_MInst_s8s8 <"combine", int_hexagon_A2_combineii>;
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// ALU32 / PERM / Mux.
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def HEXAGON_C2_mux:
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si_ALU32_qisisi <"mux", int_hexagon_C2_mux>;
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// ALU32 / PERM / Shift halfword.
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def HEXAGON_A2_aslh:
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si_ALU32_si <"aslh", int_hexagon_A2_aslh>;
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def HEXAGON_A2_asrh:
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si_ALU32_si <"asrh", int_hexagon_A2_asrh>;
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def SI_to_SXTHI_asrh:
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si_ALU32_si <"asrh", int_hexagon_SI_to_SXTHI_asrh>;
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// ALU32 / PERM / Sign/zero extend.
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def HEXAGON_A2_sxth:
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si_ALU32_si <"sxth", int_hexagon_A2_sxth>;
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def HEXAGON_A2_sxtb:
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si_ALU32_si <"sxtb", int_hexagon_A2_sxtb>;
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def HEXAGON_A2_zxth:
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si_ALU32_si <"zxth", int_hexagon_A2_zxth>;
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def HEXAGON_A2_zxtb:
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si_ALU32_si <"zxtb", int_hexagon_A2_zxtb>;
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/********************************************************************
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* ALU32/PRED *
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*********************************************************************/
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@ -2656,12 +2670,6 @@ def HEXAGON_A2_svsubuhs:
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* ALU64/ALU *
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*********************************************************************/
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// ALU64 / ALU / Add.
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def HEXAGON_A2_addp:
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di_ALU64_didi <"add", int_hexagon_A2_addp>;
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def HEXAGON_A2_addsat:
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si_ALU64_sisi_sat <"add", int_hexagon_A2_addsat>;
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// ALU64 / ALU / Compare.
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def HEXAGON_C2_cmpeqp:
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qi_ALU64_didi <"cmp.eq", int_hexagon_C2_cmpeqp>;
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@ -2670,40 +2678,10 @@ def HEXAGON_C2_cmpgtp:
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def HEXAGON_C2_cmpgtup:
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qi_ALU64_didi <"cmp.gtu", int_hexagon_C2_cmpgtup>;
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// ALU64 / ALU / Logical operations.
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def HEXAGON_A2_andp:
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di_ALU64_didi <"and", int_hexagon_A2_andp>;
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def HEXAGON_A2_orp:
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di_ALU64_didi <"or", int_hexagon_A2_orp>;
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def HEXAGON_A2_xorp:
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di_ALU64_didi <"xor", int_hexagon_A2_xorp>;
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// ALU64 / ALU / Subtract.
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def HEXAGON_A2_subp:
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di_ALU64_didi <"sub", int_hexagon_A2_subp>;
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def HEXAGON_A2_subsat:
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si_ALU64_sisi_sat <"sub", int_hexagon_A2_subsat>;
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// ALU64 / ALU / Transfer register.
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def HEXAGON_A2_tfrp:
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di_ALU64_di <"", int_hexagon_A2_tfrp>;
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/********************************************************************
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* ALU64/BIT *
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*********************************************************************/
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// ALU64 / BIT / Masked parity.
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def HEXAGON_S2_parityp:
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si_ALU64_didi <"parity", int_hexagon_S2_parityp>;
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/********************************************************************
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* ALU64/PERM *
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*********************************************************************/
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// ALU64 / PERM / Vector pack high and low halfwords.
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def HEXAGON_S2_packhl:
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di_ALU64_sisi <"packhl", int_hexagon_S2_packhl>;
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/********************************************************************
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* ALU64/VB *
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*********************************************************************/
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@ -2891,30 +2869,12 @@ def HEXAGON_C2_xor:
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* MTYPE/ALU *
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*********************************************************************/
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// MTYPE / ALU / Add and accumulate.
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def HEXAGON_M2_acci:
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si_MInst_sisisi_acc <"add", int_hexagon_M2_acci>;
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def HEXAGON_M2_accii:
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si_MInst_sisis8_acc <"add", int_hexagon_M2_accii>;
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def HEXAGON_M2_nacci:
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si_MInst_sisisi_nac <"add", int_hexagon_M2_nacci>;
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def HEXAGON_M2_naccii:
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si_MInst_sisis8_nac <"add", int_hexagon_M2_naccii>;
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// MTYPE / ALU / Subtract and accumulate.
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def HEXAGON_M2_subacc:
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si_MInst_sisisi_acc <"sub", int_hexagon_M2_subacc>;
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// MTYPE / ALU / Vector absolute difference.
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def HEXAGON_M2_vabsdiffh:
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di_MInst_didi <"vabsdiffh",int_hexagon_M2_vabsdiffh>;
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def HEXAGON_M2_vabsdiffw:
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di_MInst_didi <"vabsdiffw",int_hexagon_M2_vabsdiffw>;
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// MTYPE / ALU / XOR and xor with destination.
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def HEXAGON_M2_xor_xacc:
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si_MInst_sisisi_xacc <"xor", int_hexagon_M2_xor_xacc>;
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/********************************************************************
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* MTYPE/COMPLEX *
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@ -3014,23 +2974,6 @@ def HEXAGON_M2_vrcmacr_s0c:
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* MTYPE/MPYH *
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*********************************************************************/
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// MTYPE / MPYH / Multiply and use lower result.
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//def HEXAGON_M2_mpysmi:
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//FIXME: Hexagon_M2_mpysmi should really by of the type si_MInst_sim9,
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// not si_MInst_sis9 - but for now, we will use s9.
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// def Hexagon_M2_mpysmi:
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// si_MInst_sim9 <"mpyi", int_hexagon_M2_mpysmi>;
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def Hexagon_M2_mpysmi:
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si_MInst_sis9 <"mpyi", int_hexagon_M2_mpysmi>;
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def HEXAGON_M2_mpyi:
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si_MInst_sisi <"mpyi", int_hexagon_M2_mpyi>;
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def HEXAGON_M2_macsip:
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si_MInst_sisiu8_acc <"mpyi", int_hexagon_M2_macsip>;
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def HEXAGON_M2_maci:
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si_MInst_sisisi_acc <"mpyi", int_hexagon_M2_maci>;
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def HEXAGON_M2_macsin:
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si_MInst_sisiu8_nac <"mpyi", int_hexagon_M2_macsin>;
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// MTYPE / MPYH / Multiply word by half (32x16).
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//Rdd[+]=vmpywoh(Rss,Rtt)[:<<1][:rnd][:sat]
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//Rdd[+]=vmpyweh(Rss,Rtt)[:<<1][:rnd][:sat]
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@ -3176,112 +3119,6 @@ def HEXAGON_M2_vrmpy_s0:
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def HEXAGON_M2_vrmac_s0:
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di_MInst_dididi_acc <"vrmpyh", int_hexagon_M2_vrmac_s0>;
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/********************************************************************
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* STYPE/ALU *
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*********************************************************************/
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// STYPE / ALU / Absolute value.
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def HEXAGON_A2_abs:
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si_SInst_si <"abs", int_hexagon_A2_abs>;
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def HEXAGON_A2_abssat:
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si_SInst_si_sat <"abs", int_hexagon_A2_abssat>;
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// STYPE / ALU / Sign extend word to doubleword.
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def HEXAGON_A2_sxtw:
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di_SInst_si <"sxtw", int_hexagon_A2_sxtw>;
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/********************************************************************
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* STYPE/BIT *
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*********************************************************************/
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// STYPE / BIT / Count leading.
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def HEXAGON_S2_cl0:
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si_SInst_si <"cl0", int_hexagon_S2_cl0>;
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def HEXAGON_S2_cl0p:
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si_SInst_di <"cl0", int_hexagon_S2_cl0p>;
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def HEXAGON_S2_cl1:
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si_SInst_si <"cl1", int_hexagon_S2_cl1>;
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def HEXAGON_S2_cl1p:
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si_SInst_di <"cl1", int_hexagon_S2_cl1p>;
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def HEXAGON_S2_clb:
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si_SInst_si <"clb", int_hexagon_S2_clb>;
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def HEXAGON_S2_clbp:
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si_SInst_di <"clb", int_hexagon_S2_clbp>;
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def HEXAGON_S2_clbnorm:
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si_SInst_si <"normamt", int_hexagon_S2_clbnorm>;
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// STYPE / BIT / Count trailing.
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def HEXAGON_S2_ct0:
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si_SInst_si <"ct0", int_hexagon_S2_ct0>;
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def HEXAGON_S2_ct1:
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si_SInst_si <"ct1", int_hexagon_S2_ct1>;
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// STYPE / BIT / Compare bit mask.
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def Hexagon_C2_bitsclr:
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qi_SInst_sisi <"bitsclr", int_hexagon_C2_bitsclr>;
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def Hexagon_C2_bitsclri:
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qi_SInst_siu6 <"bitsclr", int_hexagon_C2_bitsclri>;
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def Hexagon_C2_bitsset:
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qi_SInst_sisi <"bitsset", int_hexagon_C2_bitsset>;
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// STYPE / BIT / Extract unsigned.
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// Rd[d][32/64]=extractu(Rs[s],Rt[t],[imm])
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def HEXAGON_S2_extractu:
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si_SInst_siu5u5 <"extractu",int_hexagon_S2_extractu>;
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def HEXAGON_S2_extractu_rp:
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si_SInst_sidi <"extractu",int_hexagon_S2_extractu_rp>;
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def HEXAGON_S2_extractup:
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di_SInst_diu6u6 <"extractu",int_hexagon_S2_extractup>;
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def HEXAGON_S2_extractup_rp:
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di_SInst_didi <"extractu",int_hexagon_S2_extractup_rp>;
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// STYPE / BIT / Insert bitfield.
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def Hexagon_S2_insert:
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si_SInst_sisiu5u5 <"insert", int_hexagon_S2_insert>;
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def Hexagon_S2_insert_rp:
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si_SInst_sisidi <"insert", int_hexagon_S2_insert_rp>;
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def Hexagon_S2_insertp:
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di_SInst_didiu6u6 <"insert", int_hexagon_S2_insertp>;
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def Hexagon_S2_insertp_rp:
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di_SInst_dididi <"insert", int_hexagon_S2_insertp_rp>;
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// STYPE / BIT / Innterleave/deinterleave.
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def Hexagon_S2_interleave:
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di_SInst_di <"interleave", int_hexagon_S2_interleave>;
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def Hexagon_S2_deinterleave:
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di_SInst_di <"deinterleave", int_hexagon_S2_deinterleave>;
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// STYPE / BIT / Linear feedback-shift Iteration.
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def Hexagon_S2_lfsp:
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di_SInst_didi <"lfs", int_hexagon_S2_lfsp>;
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// STYPE / BIT / Bit reverse.
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def Hexagon_S2_brev:
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si_SInst_si <"brev", int_hexagon_S2_brev>;
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// STYPE / BIT / Set/Clear/Toggle Bit.
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def HEXAGON_S2_setbit_i:
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si_SInst_siu5 <"setbit", int_hexagon_S2_setbit_i>;
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def HEXAGON_S2_togglebit_i:
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si_SInst_siu5 <"togglebit", int_hexagon_S2_togglebit_i>;
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def HEXAGON_S2_clrbit_i:
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si_SInst_siu5 <"clrbit", int_hexagon_S2_clrbit_i>;
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def HEXAGON_S2_setbit_r:
|
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si_SInst_sisi <"setbit", int_hexagon_S2_setbit_r>;
|
||||
def HEXAGON_S2_togglebit_r:
|
||||
si_SInst_sisi <"togglebit", int_hexagon_S2_togglebit_r>;
|
||||
def HEXAGON_S2_clrbit_r:
|
||||
si_SInst_sisi <"clrbit", int_hexagon_S2_clrbit_r>;
|
||||
|
||||
// STYPE / BIT / Test Bit.
|
||||
def HEXAGON_S2_tstbit_i:
|
||||
qi_SInst_siu5 <"tstbit", int_hexagon_S2_tstbit_i>;
|
||||
def HEXAGON_S2_tstbit_r:
|
||||
qi_SInst_sisi <"tstbit", int_hexagon_S2_tstbit_r>;
|
||||
|
||||
|
||||
/********************************************************************
|
||||
* STYPE/COMPLEX *
|
||||
*********************************************************************/
|
||||
@ -3299,22 +3136,6 @@ def HEXAGON_S2_vcrotate:
|
||||
* STYPE/PERM *
|
||||
*********************************************************************/
|
||||
|
||||
// STYPE / PERM / Saturate.
|
||||
def HEXAGON_A2_sat:
|
||||
si_SInst_di <"sat", int_hexagon_A2_sat>;
|
||||
def HEXAGON_A2_satb:
|
||||
si_SInst_si <"satb", int_hexagon_A2_satb>;
|
||||
def HEXAGON_A2_sath:
|
||||
si_SInst_si <"sath", int_hexagon_A2_sath>;
|
||||
def HEXAGON_A2_satub:
|
||||
si_SInst_si <"satub", int_hexagon_A2_satub>;
|
||||
def HEXAGON_A2_satuh:
|
||||
si_SInst_si <"satuh", int_hexagon_A2_satuh>;
|
||||
|
||||
// STYPE / PERM / Swizzle bytes.
|
||||
def HEXAGON_A2_swiz:
|
||||
si_SInst_si <"swiz", int_hexagon_A2_swiz>;
|
||||
|
||||
// STYPE / PERM / Vector align.
|
||||
// Need custom lowering
|
||||
def HEXAGON_S2_valignib:
|
||||
@ -3417,16 +3238,6 @@ def HEXAGON_C2_tfrrp:
|
||||
def HEXAGON_C2_vitpack:
|
||||
si_SInst_qiqi <"vitpack",int_hexagon_C2_vitpack>;
|
||||
|
||||
// STYPE / SHIFT / Table Index.
|
||||
def Hexagon_S2_tableidxb_goodsyntax:
|
||||
si_MInst_sisiu4u5 <"tableidxb",int_hexagon_S2_tableidxb_goodsyntax>;
|
||||
def Hexagon_S2_tableidxd_goodsyntax:
|
||||
si_MInst_sisiu4u5 <"tableidxd",int_hexagon_S2_tableidxd_goodsyntax>;
|
||||
def Hexagon_S2_tableidxh_goodsyntax:
|
||||
si_MInst_sisiu4u5 <"tableidxh",int_hexagon_S2_tableidxh_goodsyntax>;
|
||||
def Hexagon_S2_tableidxw_goodsyntax:
|
||||
si_MInst_sisiu4u5 <"tableidxw",int_hexagon_S2_tableidxw_goodsyntax>;
|
||||
|
||||
|
||||
/********************************************************************
|
||||
* STYPE/VH *
|
||||
|
||||
@ -14,8 +14,8 @@
|
||||
def : Pat <(mul DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(i64
|
||||
(A2_combinew
|
||||
(HEXAGON_M2_maci
|
||||
(HEXAGON_M2_maci
|
||||
(M2_maci
|
||||
(M2_maci
|
||||
(i32
|
||||
(EXTRACT_SUBREG
|
||||
(i64
|
||||
|
||||
@ -343,6 +343,12 @@ def u5ImmPred : PatLeaf<(i32 imm), [{
|
||||
return isUInt<5>(v);
|
||||
}]>;
|
||||
|
||||
def u4ImmPred : PatLeaf<(i32 imm), [{
|
||||
// u4ImmPred predicate - True if the immediate fits in a 4-bit unsigned
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<4>(v);
|
||||
}]>;
|
||||
|
||||
def u3ImmPred : PatLeaf<(i32 imm), [{
|
||||
// u3ImmPred predicate - True if the immediate fits in a 3-bit unsigned
|
||||
|
||||
@ -312,18 +312,18 @@ define i32 @S2_tableidxh_goodsyntax(i32 %a, i32 %b) {
|
||||
%z = call i32 @llvm.hexagon.S2.tableidxh.goodsyntax(i32 %a, i32 %b, i32 0, i32 0)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = tableidxh(r1, #0, #0)
|
||||
; CHECK: r0 = tableidxh(r1, #0, #-1)
|
||||
|
||||
declare i32 @llvm.hexagon.S2.tableidxw.goodsyntax(i32, i32, i32, i32)
|
||||
define i32 @S2_tableidxw_goodsyntax(i32 %a, i32 %b) {
|
||||
%z = call i32 @llvm.hexagon.S2.tableidxw.goodsyntax(i32 %a, i32 %b, i32 0, i32 0)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = tableidxw(r1, #0, #0)
|
||||
; CHECK: r0 = tableidxw(r1, #0, #-2)
|
||||
|
||||
declare i32 @llvm.hexagon.S2.tableidxd.goodsyntax(i32, i32, i32, i32)
|
||||
define i32 @S2_tableidxd_goodsyntax(i32 %a, i32 %b) {
|
||||
%z = call i32 @llvm.hexagon.S2.tableidxd.goodsyntax(i32 %a, i32 %b, i32 0, i32 0)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = tableidxd(r1, #0, #0)
|
||||
; CHECK: r0 = tableidxd(r1, #0, #-3)
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user