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post-ra-sched: Replace a std::set of regs with a bitvector.
Assuming that a single std::set node adds 3 control words, a bitvector can store (3*8+4)*8=224 registers in the allocated memory of a single element in the std::set (x86_64). Also we don't have to call malloc for every register added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151269 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -45,7 +45,6 @@
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/Statistic.h"
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#include <set>
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using namespace llvm;
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STATISTIC(NumNoops, "Number of noops inserted");
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@ -446,7 +445,7 @@ bool SchedulePostRATDList::ToggleKillFlag(MachineInstr *MI,
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void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
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DEBUG(dbgs() << "Fixup kills for BB#" << MBB->getNumber() << '\n');
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std::set<unsigned> killedRegs;
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BitVector killedRegs(TRI->getNumRegs());
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BitVector ReservedRegs = TRI->getReservedRegs(MF);
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StartBlockForKills(MBB);
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@ -487,7 +486,7 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
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// Examine all used registers and set/clear kill flag. When a
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// register is used multiple times we only set the kill flag on
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// the first use.
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killedRegs.clear();
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killedRegs.reset();
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isUse()) continue;
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@ -495,7 +494,7 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
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if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
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bool kill = false;
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if (killedRegs.find(Reg) == killedRegs.end()) {
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if (!killedRegs.test(Reg)) {
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kill = true;
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// A register is not killed if any subregs are live...
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for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
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@ -519,7 +518,7 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
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DEBUG(MI->dump());
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}
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killedRegs.insert(Reg);
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killedRegs.set(Reg);
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}
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// Mark any used register (that is not using undef) and subregs as
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