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Switch MRI::UsedPhysRegs to a register unit bit vector.

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This is a more compact, less redundant representation, and it avoids
scanning long lists of aliases for ARM D-registers, for example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166124 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-10-17 20:26:33 +00:00
parent b08c1de748
commit 4b1aa961fd
2 changed files with 19 additions and 11 deletions
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26
include/llvm/CodeGen/MachineRegisterInfo.h
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@ -77,16 +77,20 @@ class MachineRegisterInfo {
return MO->Contents.Reg.Next; return MO->Contents.Reg.Next;
} }
/// UsedPhysRegs - This is a bit vector that is computed and set by the /// UsedRegUnits - This is a bit vector that is computed and set by the
/// register allocator, and must be kept up to date by passes that run after /// register allocator, and must be kept up to date by passes that run after
/// register allocation (though most don't modify this). This is used /// register allocation (though most don't modify this). This is used
/// so that the code generator knows which callee save registers to save and /// so that the code generator knows which callee save registers to save and
/// for other target specific uses. /// for other target specific uses.
/// This vector only has bits set for registers explicitly used, not their /// This vector has bits set for register units that are modified in the
/// aliases. /// current function. It doesn't include registers clobbered by function
BitVector UsedPhysRegs; /// calls with register mask operands.
BitVector UsedRegUnits;
/// UsedPhysRegMask - Additional used physregs, but including aliases. /// UsedPhysRegMask - Additional used physregs including aliases.
/// This bit vector represents all the registers clobbered by function calls.
/// It can model things that UsedRegUnits can't, such as function calls that
/// clobber ymm7 but preserve the low half in xmm7.
BitVector UsedPhysRegMask; BitVector UsedPhysRegMask;
/// ReservedRegs - This is a bit vector of reserved registers. The target /// ReservedRegs - This is a bit vector of reserved registers. The target
@ -366,15 +370,18 @@ public:
bool isPhysRegUsed(unsigned Reg) const { bool isPhysRegUsed(unsigned Reg) const {
if (UsedPhysRegMask.test(Reg)) if (UsedPhysRegMask.test(Reg))
return true; return true;
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
if (UsedPhysRegs.test(*AI)) if (UsedRegUnits.test(*Units))
return true; return true;
return false; return false;
} }
/// setPhysRegUsed - Mark the specified register used in this function. /// setPhysRegUsed - Mark the specified register used in this function.
/// This should only be called during and after register allocation. /// This should only be called during and after register allocation.
void setPhysRegUsed(unsigned Reg) { UsedPhysRegs.set(Reg); } void setPhysRegUsed(unsigned Reg) {
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
UsedRegUnits.set(*Units);
}
/// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used. /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
/// This corresponds to the bit mask attached to register mask operands. /// This corresponds to the bit mask attached to register mask operands.
@ -385,8 +392,9 @@ public:
/// setPhysRegUnused - Mark the specified register unused in this function. /// setPhysRegUnused - Mark the specified register unused in this function.
/// This should only be called during and after register allocation. /// This should only be called during and after register allocation.
void setPhysRegUnused(unsigned Reg) { void setPhysRegUnused(unsigned Reg) {
UsedPhysRegs.reset(Reg);
UsedPhysRegMask.reset(Reg); UsedPhysRegMask.reset(Reg);
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
UsedRegUnits.reset(*Units);
} }

4
lib/CodeGen/MachineRegisterInfo.cpp
View File

@ -21,7 +21,7 @@ MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI)
: TRI(&TRI), IsSSA(true), TracksLiveness(true) { : TRI(&TRI), IsSSA(true), TracksLiveness(true) {
VRegInfo.reserve(256); VRegInfo.reserve(256);
RegAllocHints.reserve(256); RegAllocHints.reserve(256);
UsedPhysRegs.resize(TRI.getNumRegs()); UsedRegUnits.resize(TRI.getNumRegUnits());
UsedPhysRegMask.resize(TRI.getNumRegs()); UsedPhysRegMask.resize(TRI.getNumRegs());
// Create the physreg use/def lists. // Create the physreg use/def lists.
@ -32,7 +32,7 @@ MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI)
MachineRegisterInfo::~MachineRegisterInfo() { MachineRegisterInfo::~MachineRegisterInfo() {
#ifndef NDEBUG #ifndef NDEBUG
clearVirtRegs(); clearVirtRegs();
for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i) for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
assert(!PhysRegUseDefLists[i] && assert(!PhysRegUseDefLists[i] &&
"PhysRegUseDefLists has entries after all instructions are deleted"); "PhysRegUseDefLists has entries after all instructions are deleted");
#endif #endif