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Shrinkify Thumb2 load / store multiple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78717 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
59fc42debd
commit
4b322e58b7
@ -1333,7 +1333,8 @@ ARMConstantIslands::FixUpConditionalBr(MachineFunction &MF, ImmBranch &Br) {
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}
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/// UndoLRSpillRestore - Remove Thumb push / pop instructions that only spills
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/// LR / restores LR to pc.
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/// LR / restores LR to pc. FIXME: This is done here because it's only possible
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/// to do this if tBfar is not used.
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bool ARMConstantIslands::UndoLRSpillRestore() {
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bool MadeChange = false;
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for (unsigned i = 0, e = PushPopMIs.size(); i != e; ++i) {
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@ -181,9 +181,9 @@ let isReturn = 1, isTerminator = 1 in {
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}
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// FIXME: remove when we have a way to marking a MI with these properties.
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let isReturn = 1, isTerminator = 1 in
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def tPOP_RET : T1I<(outs reglist:$dst1, variable_ops), (ins), IIC_Br,
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"pop $dst1", []>;
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let isReturn = 1, isTerminator = 1, mayLoad = 1 in
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def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$dst1, variable_ops), IIC_Br,
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"pop${p} $dst1", []>;
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let isCall = 1,
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Defs = [R0, R1, R2, R3, R12, LR,
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@ -347,16 +347,26 @@ def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore,
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// Load / store multiple Instructions.
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//
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// TODO: A7-44: LDMIA - load multiple
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// TODO: Allow these to be predicated
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// These requires base address to be written back or one of the loaded regs.
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let mayLoad = 1 in
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def tPOP : T1I<(outs reglist:$dst1, variable_ops), (ins), IIC_Br,
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"pop $dst1", []>;
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def tLDM : T1I<(outs),
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(ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
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IIC_iLoad,
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"ldm${addr:submode}${p} $addr, $dst1", []>;
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let mayStore = 1 in
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def tPUSH : T1I<(outs), (ins reglist:$src1, variable_ops), IIC_Br,
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"push $src1", []>;
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def tSTM : T1I<(outs),
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(ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
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IIC_iStore,
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"stm${addr:submode}${p} $addr, $src1", []>;
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let mayLoad = 1, Uses = [SP], Defs = [SP] in
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def tPOP : T1I<(outs), (ins pred:$p, reglist:$dst1, variable_ops), IIC_Br,
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"pop${p} $dst1", []>;
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let mayStore = 1, Uses = [SP], Defs = [SP] in
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def tPUSH : T1I<(outs), (ins pred:$p, reglist:$src1, variable_ops), IIC_Br,
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"push${p} $src1", []>;
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions.
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@ -1106,7 +1106,7 @@ let Defs =
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let isReturn = 1, isTerminator = 1, mayLoad = 1 in
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def t2LDM_RET : T2XI<(outs),
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(ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
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IIC_iLoad, "ldm${addr:submode}${p}${addr:wide} $addr, $dst1",
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IIC_Br, "ldm${addr:submode}${p}${addr:wide} $addr, $dst1",
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[]>;
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let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
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@ -885,8 +885,10 @@ void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
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void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
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O << "{";
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for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
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if (MI->getOperand(i).isImplicit())
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continue;
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if ((int)i != OpNum) O << ", ";
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printOperand(MI, i);
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if (i != e-1) O << ", ";
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}
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O << "}";
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}
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@ -149,6 +149,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
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AddDefaultPred(MIB);
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for (unsigned i = CSI.size(); i != 0; --i) {
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unsigned Reg = CSI[i-1].getReg();
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// Add the callee-saved register as live-in. It's killed at the spill.
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@ -168,7 +169,11 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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return false;
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bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
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MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
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DebugLoc DL = MI->getDebugLoc();
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MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
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AddDefaultPred(MIB);
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bool NumRegs = 0;
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for (unsigned i = CSI.size(); i != 0; --i) {
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unsigned Reg = CSI[i-1].getReg();
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if (Reg == ARM::LR) {
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@ -176,15 +181,16 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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if (isVarArg)
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continue;
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Reg = ARM::PC;
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PopMI->setDesc(get(ARM::tPOP_RET));
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(*MIB).setDesc(get(ARM::tPOP_RET));
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MI = MBB.erase(MI);
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}
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PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
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MIB.addReg(Reg, getDefRegState(true));
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++NumRegs;
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}
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// It's illegal to emit pop instruction without operands.
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if (PopMI->getNumOperands() > 0)
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MBB.insert(MI, PopMI);
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if (NumRegs)
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MBB.insert(MI, &*MIB);
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return true;
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}
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@ -834,7 +834,7 @@ void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
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if (VARegSaveSize) {
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// Epilogue for vararg functions: pop LR to R3 and branch off it.
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// FIXME: Verify this is still ok when R3 is no longer being reserved.
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)).addReg(ARM::R3);
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AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))).addReg(ARM::R3);
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emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
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@ -9,6 +9,7 @@
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#define DEBUG_TYPE "t2-reduce-size"
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#include "ARM.h"
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#include "ARMAddressingModes.h"
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#include "ARMBaseRegisterInfo.h"
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#include "ARMBaseInstrInfo.h"
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#include "Thumb2InstrInfo.h"
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@ -26,7 +27,12 @@ STATISTIC(NumNarrows, "Number of 32-bit instrs reduced to 16-bit ones");
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STATISTIC(Num2Addrs, "Number of 32-bit instrs reduced to 2addr 16-bit ones");
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STATISTIC(NumLdSts, "Number of 32-bit load / store reduced to 16-bit ones");
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static cl::opt<int> ReduceLimit("t2-reduce-limit", cl::init(-1), cl::Hidden);
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static cl::opt<int> ReduceLimit("t2-reduce-limit",
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cl::init(-1), cl::Hidden);
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static cl::opt<int> ReduceLimit2Addr("t2-reduce-limit2",
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cl::init(-1), cl::Hidden);
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static cl::opt<int> ReduceLimitLdSt("t2-reduce-limit3",
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cl::init(-1), cl::Hidden);
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namespace {
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/// ReduceTable - A static table with information on mapping from wide
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@ -101,7 +107,11 @@ namespace {
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{ ARM::t2STRBi12,ARM::tSTRB, 0, 5, 0, 1, 0, 0,0, 1 },
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{ ARM::t2STRBs, ARM::tSTRB, 0, 0, 0, 1, 0, 0,0, 1 },
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{ ARM::t2STRHi12,ARM::tSTRH, 0, 5, 0, 1, 0, 0,0, 1 },
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{ ARM::t2STRHs, ARM::tSTRH, 0, 0, 0, 1, 0, 0,0, 1 }
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{ ARM::t2STRHs, ARM::tSTRH, 0, 0, 0, 1, 0, 0,0, 1 },
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{ ARM::t2LDM_RET,0, ARM::tPOP_RET, 0, 0, 1, 1, 1,1, 1 },
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{ ARM::t2LDM, ARM::tLDM, ARM::tPOP, 0, 0, 1, 1, 1,1, 1 },
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{ ARM::t2STM, ARM::tSTM, ARM::tPUSH, 0, 0, 1, 1, 1,1, 1 },
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};
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class VISIBILITY_HIDDEN Thumb2SizeReduce : public MachineFunctionPass {
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@ -185,12 +195,43 @@ static bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
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return true;
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}
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static bool VerifyLowRegs(MachineInstr *MI) {
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unsigned Opc = MI->getOpcode();
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bool isPCOk = (Opc == ARM::t2LDM_RET) || (Opc == ARM::t2LDM);
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bool isLROk = (Opc == ARM::t2STM);
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bool isSPOk = isPCOk || isLROk;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || MO.isImplicit())
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continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0 || Reg == ARM::CPSR)
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continue;
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if (isPCOk && Reg == ARM::PC)
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continue;
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if (isLROk && Reg == ARM::LR)
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continue;
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if (isSPOk && Reg == ARM::SP)
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continue;
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if (!isARMLowRegister(Reg))
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return false;
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}
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return true;
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}
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bool
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Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry) {
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if (ReduceLimitLdSt != -1 && ((int)NumLdSts >= ReduceLimitLdSt))
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return false;
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unsigned Scale = 1;
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bool HasImmOffset = false;
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bool HasShift = false;
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bool isLdStMul = false;
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bool isPopPush = false;
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unsigned Opc = Entry.NarrowOpc1;
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unsigned OpNum = 3; // First 'rest' of operands.
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switch (Entry.WideOpc) {
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default:
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llvm_unreachable("Unexpected Thumb2 load / store opcode!");
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@ -217,7 +258,27 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
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case ARM::t2STRBs:
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case ARM::t2STRHs:
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HasShift = true;
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OpNum = 4;
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break;
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case ARM::t2LDM_RET:
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case ARM::t2LDM:
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case ARM::t2STM: {
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OpNum = 0;
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unsigned BaseReg = MI->getOperand(0).getReg();
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unsigned Mode = MI->getOperand(1).getImm();
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if (BaseReg == ARM::SP && ARM_AM::getAM4WBFlag(Mode)) {
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Opc = Entry.NarrowOpc2;
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isPopPush = true;
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OpNum = 2;
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} else if (Entry.WideOpc == ARM::t2LDM_RET ||
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!isARMLowRegister(BaseReg) ||
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!ARM_AM::getAM4WBFlag(Mode) ||
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ARM_AM::getAM4SubMode(Mode) != ARM_AM::ia) {
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return false;
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}
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isLdStMul = true;
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break;
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}
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}
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unsigned OffsetReg = 0;
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@ -242,22 +303,21 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
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// Add the 16-bit load / store instruction.
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// FIXME: Thumb1 addressing mode encode both immediate and register offset.
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DebugLoc dl = MI->getDebugLoc();
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MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Entry.NarrowOpc1))
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.addOperand(MI->getOperand(0))
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.addOperand(MI->getOperand(1));
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if (Entry.NarrowOpc1 != ARM::tLDRSB && Entry.NarrowOpc1 != ARM::tLDRSH) {
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// tLDRSB and tLDRSH do not have an immediate offset field. On the other
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// hand, it must have an offset register.
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// FIXME: Remove this special case.
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MIB.addImm(OffsetImm/Scale);
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MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc));
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if (!isLdStMul) {
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MIB.addOperand(MI->getOperand(0)).addOperand(MI->getOperand(1));
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if (Entry.NarrowOpc1 != ARM::tLDRSB && Entry.NarrowOpc1 != ARM::tLDRSH) {
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// tLDRSB and tLDRSH do not have an immediate offset field. On the other
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// hand, it must have an offset register.
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// FIXME: Remove this special case.
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MIB.addImm(OffsetImm/Scale);
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}
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assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
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MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
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}
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assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
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MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
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// Transfer the rest of operands.
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unsigned OpNum = HasShift ? 4 : 3;
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for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
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MIB.addOperand(MI->getOperand(OpNum));
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@ -268,28 +328,14 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
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return true;
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}
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static bool VerifyLowRegs(MachineInstr *MI, const TargetInstrDesc &TID) {
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for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0 || Reg == ARM::CPSR)
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continue;
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if (!isARMLowRegister(Reg))
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return false;
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}
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return true;
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}
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bool
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Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry,
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bool LiveCPSR) {
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const TargetInstrDesc &TID = MI->getDesc();
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if (Entry.LowRegs1 && !VerifyLowRegs(MI, TID))
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if (Entry.LowRegs1 && !VerifyLowRegs(MI))
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return false;
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const TargetInstrDesc &TID = MI->getDesc();
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if (TID.mayLoad() || TID.mayStore())
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return ReduceLoadStore(MBB, MI, Entry);
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return false;
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@ -299,6 +345,10 @@ bool
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Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry,
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bool LiveCPSR) {
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if (ReduceLimit2Addr != -1 && ((int)Num2Addrs >= ReduceLimit2Addr))
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return false;
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const TargetInstrDesc &TID = MI->getDesc();
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unsigned Reg0 = MI->getOperand(0).getReg();
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unsigned Reg1 = MI->getOperand(1).getReg();
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@ -369,6 +419,9 @@ bool
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Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry,
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bool LiveCPSR) {
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if (ReduceLimit != -1 && ((int)NumNarrows >= ReduceLimit))
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return false;
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unsigned Limit = ~0U;
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if (Entry.Imm1Limit)
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Limit = (1 << Entry.Imm1Limit) - 1;
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@ -511,9 +564,6 @@ bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
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ProcessNext:
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LiveCPSR = UpdateCPSRLiveness(*MI, LiveCPSR);
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if (ReduceLimit != -1 && ((int)(NumNarrows + Num2Addrs) > ReduceLimit))
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break;
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}
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return Modified;
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@ -4,8 +4,8 @@
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define i32 @t1() {
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; CHECK: t1:
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; CHECK: stmfd sp!, {r7, lr}
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; CHECK: ldmfd.w sp!, {r7, pc}
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; CHECK: push {r7, lr}
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; CHECK: pop {r7, pc}
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%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0) ; <i32> [#uses=1]
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%tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1]
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%tmp4 = tail call i32 @f1( i32 %tmp, i32 %tmp3 ) ; <i32> [#uses=1]
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@ -14,9 +14,9 @@ define i32 @t1() {
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define i32 @t2() {
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; CHECK: t2:
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; CHECK: stmfd sp!, {r7, lr}
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; CHECK: ldmia.w
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; CHECK: ldmfd.w sp!, {r7, pc}
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; CHECK: push {r7, lr}
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; CHECK: ldmia
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; CHECK: pop {r7, pc}
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%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1]
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%tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1]
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%tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 4) ; <i32> [#uses=1]
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@ -26,8 +26,8 @@ define i32 @t2() {
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define i32 @t3() {
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; CHECK: t3:
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; CHECK: stmfd sp!, {r7, lr}
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; CHECK: ldmfd.w sp!, {r7, pc}
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; CHECK: push {r7, lr}
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; CHECK: pop {r7, pc}
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%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1]
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%tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1]
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%tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1]
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