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AMDGPU: Run fp combine tests on VI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290192 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
44e57608d4
commit
4bcae756d4
@ -1,17 +1,26 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; Make sure (fmul (fadd x, x), c) -> (fmul x, (fmul 2.0, c)) doesn't
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; make add an instruction if the fadd has more than one use.
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declare float @llvm.fabs.f32(float) #1
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; GCN-LABEL: {{^}}multiple_fadd_use_test:
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; GCN: v_max_legacy_f32_e64 [[A16:v[0-9]+]],
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; GCN: v_add_f32_e32 [[A17:v[0-9]+]], [[A16]], [[A16]]
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; GCN: v_mul_f32_e32 [[A18:v[0-9]+]], [[A17]], [[A17]]
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; GCN: v_mad_f32 [[A20:v[0-9]+]], -[[A18]], [[A17]], 1.0
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; GCN: buffer_store_dword [[A20]]
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define void @multiple_fadd_use_test(float addrspace(1)* %out, float %x, float %y, float %z) #0 {
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; GCN-LABEL: {{^}}multiple_fadd_use_test_f32:
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; SI: v_max_legacy_f32_e64 [[A16:v[0-9]+]],
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; SI: v_add_f32_e32 [[A17:v[0-9]+]], [[A16]], [[A16]]
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; SI: v_mul_f32_e32 [[A18:v[0-9]+]], [[A17]], [[A17]]
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; SI: v_mad_f32 [[A20:v[0-9]+]], -[[A18]], [[A17]], 1.0
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; SI: buffer_store_dword [[A20]]
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; VI: v_add_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, -1.0
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; VI: v_add_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, -1.0
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; VI: v_cmp_gt_f32_e64 vcc, |v{{[0-9]+}}|, |v{{[0-9]+}}|
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; VI: v_cndmask_b32_e32
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; VI: v_add_f32_e32
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; VI: v_mul_f32_e32
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; VI: v_mad_f32 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, 1.0
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define void @multiple_fadd_use_test_f32(float addrspace(1)* %out, float %x, float %y, float %z) #0 {
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%a11 = fadd fast float %y, -1.0
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%a12 = call float @llvm.fabs.f32(float %a11)
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%a13 = fadd fast float %x, -1.0
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@ -26,13 +35,13 @@ define void @multiple_fadd_use_test(float addrspace(1)* %out, float %x, float %y
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ret void
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}
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; GCN-LABEL: {{^}}multiple_use_fadd_fmac
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; GCN-LABEL: {{^}}multiple_use_fadd_fmac_f32:
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; GCN-DAG: v_add_f32_e64 [[MUL2:v[0-9]+]], [[X:s[0-9]+]], s{{[0-9]+}}
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; GCN-DAG: v_mac_f32_e64 [[MAD:v[0-9]+]], 2.0, [[X]]
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; GCN-DAG: buffer_store_dword [[MUL2]]
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; GCN-DAG: buffer_store_dword [[MAD]]
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; GCN: s_endpgm
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define void @multiple_use_fadd_fmac(float addrspace(1)* %out, float %x, float %y) #0 {
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define void @multiple_use_fadd_fmac_f32(float addrspace(1)* %out, float %x, float %y) #0 {
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%out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1
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%mul2 = fmul fast float %x, 2.0
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%mad = fadd fast float %mul2, %y
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@ -41,13 +50,13 @@ define void @multiple_use_fadd_fmac(float addrspace(1)* %out, float %x, float %y
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ret void
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}
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; GCN-LABEL: {{^}}multiple_use_fadd_fmad:
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; GCN-LABEL: {{^}}multiple_use_fadd_fmad_f32:
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; GCN-DAG: v_add_f32_e64 [[MUL2:v[0-9]+]], |[[X:s[0-9]+]]|, |s{{[0-9]+}}|
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; GCN-DAG: v_mad_f32 [[MAD:v[0-9]+]], 2.0, |[[X]]|, v{{[0-9]+}}
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; GCN-DAG: buffer_store_dword [[MUL2]]
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; GCN-DAG: buffer_store_dword [[MAD]]
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; GCN: s_endpgm
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define void @multiple_use_fadd_fmad(float addrspace(1)* %out, float %x, float %y) #0 {
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define void @multiple_use_fadd_fmad_f32(float addrspace(1)* %out, float %x, float %y) #0 {
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%out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1
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%x.abs = call float @llvm.fabs.f32(float %x)
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%mul2 = fmul fast float %x.abs, 2.0
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@ -57,10 +66,10 @@ define void @multiple_use_fadd_fmad(float addrspace(1)* %out, float %x, float %y
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ret void
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}
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; GCN-LABEL: {{^}}multiple_use_fadd_multi_fmad:
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; GCN-LABEL: {{^}}multiple_use_fadd_multi_fmad_f32:
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; GCN: v_mad_f32 {{v[0-9]+}}, 2.0, |[[X:s[0-9]+]]|, v{{[0-9]+}}
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; GCN: v_mad_f32 {{v[0-9]+}}, 2.0, |[[X]]|, v{{[0-9]+}}
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define void @multiple_use_fadd_multi_fmad(float addrspace(1)* %out, float %x, float %y, float %z) #0 {
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define void @multiple_use_fadd_multi_fmad_f32(float addrspace(1)* %out, float %x, float %y, float %z) #0 {
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%out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1
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%x.abs = call float @llvm.fabs.f32(float %x)
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%mul2 = fmul fast float %x.abs, 2.0
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@ -71,11 +80,11 @@ define void @multiple_use_fadd_multi_fmad(float addrspace(1)* %out, float %x, fl
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ret void
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}
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; GCN-LABEL: {{^}}fmul_x2_xn2:
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; GCN-LABEL: {{^}}fmul_x2_xn2_f32:
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; GCN: v_mul_f32_e64 [[TMP0:v[0-9]+]], [[X:s[0-9]+]], -4.0
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; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], [[X]], [[TMP0]]
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; GCN: buffer_store_dword [[RESULT]]
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define void @fmul_x2_xn2(float addrspace(1)* %out, float %x, float %y) #0 {
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define void @fmul_x2_xn2_f32(float addrspace(1)* %out, float %x, float %y) #0 {
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%out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1
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%mul2 = fmul fast float %x, 2.0
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%muln2 = fmul fast float %x, -2.0
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@ -84,12 +93,12 @@ define void @fmul_x2_xn2(float addrspace(1)* %out, float %x, float %y) #0 {
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ret void
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}
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; GCN-LABEL: {{^}}fmul_x2_xn3:
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; GCN-LABEL: {{^}}fmul_x2_xn3_f32:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0xc0c00000
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; GCN: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[X:s[0-9]+]], [[K]]
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; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], [[X]], [[TMP0]]
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; GCN: buffer_store_dword [[RESULT]]
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define void @fmul_x2_xn3(float addrspace(1)* %out, float %x, float %y) #0 {
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define void @fmul_x2_xn3_f32(float addrspace(1)* %out, float %x, float %y) #0 {
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%out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1
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%mul2 = fmul fast float %x, 2.0
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%muln2 = fmul fast float %x, -3.0
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@ -1,42 +1,43 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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declare float @llvm.fmuladd.f32(float, float, float)
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declare double @llvm.fmuladd.f64(double, double, double)
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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declare float @llvm.fabs.f32(float) nounwind readnone
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; CHECK-LABEL: {{^}}fmuladd_f32:
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; CHECK: v_mac_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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define void @fmuladd_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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float addrspace(1)* %in2, float addrspace(1)* %in3) {
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%r0 = load float, float addrspace(1)* %in1
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%r1 = load float, float addrspace(1)* %in2
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%r2 = load float, float addrspace(1)* %in3
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%r3 = tail call float @llvm.fmuladd.f32(float %r0, float %r1, float %r2)
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store float %r3, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}fmuladd_f64:
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; CHECK: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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declare double @llvm.fmuladd.f64(double, double, double) #1
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare float @llvm.fabs.f32(float) #1
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declare float @llvm.fmuladd.f32(float, float, float) #1
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; GCN-LABEL: {{^}}fmuladd_f64:
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; GCN: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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define void @fmuladd_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2, double addrspace(1)* %in3) {
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%r0 = load double, double addrspace(1)* %in1
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%r1 = load double, double addrspace(1)* %in2
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%r2 = load double, double addrspace(1)* %in3
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%r3 = tail call double @llvm.fmuladd.f64(double %r0, double %r1, double %r2)
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store double %r3, double addrspace(1)* %out
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ret void
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double addrspace(1)* %in2, double addrspace(1)* %in3) #0 {
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%r0 = load double, double addrspace(1)* %in1
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%r1 = load double, double addrspace(1)* %in2
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%r2 = load double, double addrspace(1)* %in3
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%r3 = tail call double @llvm.fmuladd.f64(double %r0, double %r1, double %r2)
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store double %r3, double addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}fmuladd_2.0_a_b_f32
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; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; CHECK: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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; CHECK: buffer_store_dword [[R2]]
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define void @fmuladd_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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; GCN-LABEL: {{^}}fmuladd_f32:
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; GCN: v_mac_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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define void @fmuladd_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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float addrspace(1)* %in2, float addrspace(1)* %in3) #0 {
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%r0 = load float, float addrspace(1)* %in1
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%r1 = load float, float addrspace(1)* %in2
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%r2 = load float, float addrspace(1)* %in3
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%r3 = tail call float @llvm.fmuladd.f32(float %r0, float %r1, float %r2)
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store float %r3, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}fmuladd_2.0_a_b_f32
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; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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; GCN: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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; SI: buffer_store_dword [[R2]]
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; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
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define void @fmuladd_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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@ -50,12 +51,14 @@ define void @fmuladd_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %
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ret void
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}
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; CHECK-LABEL: {{^}}fmuladd_a_2.0_b_f32
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; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; CHECK: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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; CHECK: buffer_store_dword [[R2]]
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define void @fmuladd_a_2.0_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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; GCN-LABEL: {{^}}fmuladd_a_2.0_b_f32
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; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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; GCN: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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; SI: buffer_store_dword [[R2]]
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; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
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define void @fmuladd_a_2.0_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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@ -69,14 +72,16 @@ define void @fmuladd_a_2.0_b_f32(float addrspace(1)* %out, float addrspace(1)* %
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ret void
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}
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; CHECK-LABEL: {{^}}fadd_a_a_b_f32:
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; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; CHECK: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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; CHECK: buffer_store_dword [[R2]]
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; GCN-LABEL: {{^}}fadd_a_a_b_f32:
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; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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; GCN: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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; SI: buffer_store_dword [[R2]]
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; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
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define void @fadd_a_a_b_f32(float addrspace(1)* %out,
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float addrspace(1)* %in1,
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float addrspace(1)* %in2) {
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float addrspace(1)* %in2) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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@ -87,18 +92,20 @@ define void @fadd_a_a_b_f32(float addrspace(1)* %out,
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%add.0 = fadd float %r0, %r0
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%add.1 = fadd float %add.0, %r1
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store float %add.1, float addrspace(1)* %out
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store float %add.1, float addrspace(1)* %gep.out
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ret void
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}
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; CHECK-LABEL: {{^}}fadd_b_a_a_f32:
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; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; CHECK: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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; CHECK: buffer_store_dword [[R2]]
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; GCN-LABEL: {{^}}fadd_b_a_a_f32:
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; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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; GCN: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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; SI: buffer_store_dword [[R2]]
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; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
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define void @fadd_b_a_a_f32(float addrspace(1)* %out,
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float addrspace(1)* %in1,
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float addrspace(1)* %in2) {
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float addrspace(1)* %in2) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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@ -109,16 +116,18 @@ define void @fadd_b_a_a_f32(float addrspace(1)* %out,
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%add.0 = fadd float %r0, %r0
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%add.1 = fadd float %r1, %add.0
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store float %add.1, float addrspace(1)* %out
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store float %add.1, float addrspace(1)* %gep.out
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ret void
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}
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; CHECK-LABEL: {{^}}fmuladd_neg_2.0_a_b_f32
|
||||
; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; CHECK: v_mac_f32_e32 [[R2]], -2.0, [[R1]]
|
||||
; CHECK: buffer_store_dword [[R2]]
|
||||
define void @fmuladd_neg_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
|
||||
; GCN-LABEL: {{^}}fmuladd_neg_2.0_a_b_f32
|
||||
; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
|
||||
; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
|
||||
; GCN: v_mac_f32_e32 [[R2]], -2.0, [[R1]]
|
||||
|
||||
; SI: buffer_store_dword [[R2]]
|
||||
; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
|
||||
define void @fmuladd_neg_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
||||
%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
|
||||
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
|
||||
@ -132,13 +141,14 @@ define void @fmuladd_neg_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}fmuladd_neg_2.0_neg_a_b_f32
|
||||
; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
|
||||
; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
|
||||
; GCN: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
|
||||
|
||||
; CHECK-LABEL: {{^}}fmuladd_neg_2.0_neg_a_b_f32
|
||||
; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; CHECK: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
|
||||
; CHECK: buffer_store_dword [[R2]]
|
||||
define void @fmuladd_neg_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
|
||||
; SI: buffer_store_dword [[R2]]
|
||||
; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
|
||||
define void @fmuladd_neg_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
||||
%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
|
||||
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
|
||||
@ -154,13 +164,14 @@ define void @fmuladd_neg_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspa
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}fmuladd_2.0_neg_a_b_f32
|
||||
; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
|
||||
; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
|
||||
; GCN: v_mac_f32_e32 [[R2]], -2.0, [[R1]]
|
||||
|
||||
; CHECK-LABEL: {{^}}fmuladd_2.0_neg_a_b_f32
|
||||
; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; CHECK: v_mac_f32_e32 [[R2]], -2.0, [[R1]]
|
||||
; CHECK: buffer_store_dword [[R2]]
|
||||
define void @fmuladd_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
|
||||
; SI: buffer_store_dword [[R2]]
|
||||
; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
|
||||
define void @fmuladd_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
||||
%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
|
||||
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
|
||||
@ -176,13 +187,14 @@ define void @fmuladd_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}fmuladd_2.0_a_neg_b_f32
|
||||
; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
|
||||
; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
|
||||
; GCN: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], -[[R2]]
|
||||
|
||||
; CHECK-LABEL: {{^}}fmuladd_2.0_a_neg_b_f32
|
||||
; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], -[[R2]]
|
||||
; CHECK: buffer_store_dword [[RESULT]]
|
||||
define void @fmuladd_2.0_a_neg_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
|
||||
; SI: buffer_store_dword [[RESULT]]
|
||||
; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
|
||||
define void @fmuladd_2.0_a_neg_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
||||
%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
|
||||
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
|
||||
@ -197,3 +209,6 @@ define void @fmuladd_2.0_a_neg_b_f32(float addrspace(1)* %out, float addrspace(1
|
||||
store float %r3, float addrspace(1)* %gep.out
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind readnone }
|
||||
|
||||
@ -1,14 +1,17 @@
|
||||
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
|
||||
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
|
||||
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
|
||||
|
||||
declare i32 @llvm.amdgcn.workitem.id.x() #0
|
||||
declare float @llvm.fabs.f32(float) #0
|
||||
|
||||
; FUNC-LABEL: {{^}}mad_sub_f32:
|
||||
; SI: buffer_load_dword [[REGA:v[0-9]+]]
|
||||
; SI: buffer_load_dword [[REGB:v[0-9]+]]
|
||||
; SI: buffer_load_dword [[REGC:v[0-9]+]]
|
||||
; SI: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -[[REGC]]
|
||||
; GCN-LABEL: {{^}}mad_sub_f32:
|
||||
; GCN: {{buffer|flat}}_load_dword [[REGA:v[0-9]+]]
|
||||
; GCN: {{buffer|flat}}_load_dword [[REGB:v[0-9]+]]
|
||||
; GCN: {{buffer|flat}}_load_dword [[REGC:v[0-9]+]]
|
||||
; GCN: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -[[REGC]]
|
||||
|
||||
; SI: buffer_store_dword [[RESULT]]
|
||||
; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
|
||||
define void @mad_sub_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 {
|
||||
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
@ -27,12 +30,14 @@ define void @mad_sub_f32(float addrspace(1)* noalias nocapture %out, float addrs
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}mad_sub_inv_f32:
|
||||
; SI: buffer_load_dword [[REGA:v[0-9]+]]
|
||||
; SI: buffer_load_dword [[REGB:v[0-9]+]]
|
||||
; SI: buffer_load_dword [[REGC:v[0-9]+]]
|
||||
; SI: v_mad_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], [[REGC]]
|
||||
; GCN-LABEL: {{^}}mad_sub_inv_f32:
|
||||
; GCN: {{buffer|flat}}_load_dword [[REGA:v[0-9]+]]
|
||||
; GCN: {{buffer|flat}}_load_dword [[REGB:v[0-9]+]]
|
||||
; GCN: {{buffer|flat}}_load_dword [[REGC:v[0-9]+]]
|
||||
; GCN: v_mad_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], [[REGC]]
|
||||
|
||||
; SI: buffer_store_dword [[RESULT]]
|
||||
; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
|
||||
define void @mad_sub_inv_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 {
|
||||
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
@ -51,9 +56,9 @@ define void @mad_sub_inv_f32(float addrspace(1)* noalias nocapture %out, float a
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}mad_sub_f64:
|
||||
; SI: v_mul_f64
|
||||
; SI: v_add_f64
|
||||
; GCN-LABEL: {{^}}mad_sub_f64:
|
||||
; GCN: v_mul_f64
|
||||
; GCN: v_add_f64
|
||||
define void @mad_sub_f64(double addrspace(1)* noalias nocapture %out, double addrspace(1)* noalias nocapture readonly %ptr) #1 {
|
||||
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
@ -72,12 +77,13 @@ define void @mad_sub_f64(double addrspace(1)* noalias nocapture %out, double add
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}mad_sub_fabs_f32:
|
||||
; SI: buffer_load_dword [[REGA:v[0-9]+]]
|
||||
; SI: buffer_load_dword [[REGB:v[0-9]+]]
|
||||
; SI: buffer_load_dword [[REGC:v[0-9]+]]
|
||||
; SI: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -|[[REGC]]|
|
||||
; GCN-LABEL: {{^}}mad_sub_fabs_f32:
|
||||
; GCN: {{buffer|flat}}_load_dword [[REGA:v[0-9]+]]
|
||||
; GCN: {{buffer|flat}}_load_dword [[REGB:v[0-9]+]]
|
||||
; GCN: {{buffer|flat}}_load_dword [[REGC:v[0-9]+]]
|
||||
; GCN: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -|[[REGC]]|
|
||||
; SI: buffer_store_dword [[RESULT]]
|
||||
; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
|
||||
define void @mad_sub_fabs_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 {
|
||||
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
@ -97,12 +103,13 @@ define void @mad_sub_fabs_f32(float addrspace(1)* noalias nocapture %out, float
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}mad_sub_fabs_inv_f32:
|
||||
; SI: buffer_load_dword [[REGA:v[0-9]+]]
|
||||
; SI: buffer_load_dword [[REGB:v[0-9]+]]
|
||||
; SI: buffer_load_dword [[REGC:v[0-9]+]]
|
||||
; SI: v_mad_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], |[[REGC]]|
|
||||
; GCN-LABEL: {{^}}mad_sub_fabs_inv_f32:
|
||||
; GCN: {{buffer|flat}}_load_dword [[REGA:v[0-9]+]]
|
||||
; GCN: {{buffer|flat}}_load_dword [[REGB:v[0-9]+]]
|
||||
; GCN: {{buffer|flat}}_load_dword [[REGC:v[0-9]+]]
|
||||
; GCN: v_mad_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], |[[REGC]]|
|
||||
; SI: buffer_store_dword [[RESULT]]
|
||||
; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
|
||||
define void @mad_sub_fabs_inv_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 {
|
||||
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
@ -122,8 +129,8 @@ define void @mad_sub_fabs_inv_f32(float addrspace(1)* noalias nocapture %out, fl
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}neg_neg_mad_f32:
|
||||
; SI: v_mac_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
|
||||
; GCN-LABEL: {{^}}neg_neg_mad_f32:
|
||||
; GCN: v_mac_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
|
||||
define void @neg_neg_mad_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 {
|
||||
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
@ -144,12 +151,13 @@ define void @neg_neg_mad_f32(float addrspace(1)* noalias nocapture %out, float a
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}mad_fabs_sub_f32:
|
||||
; SI: buffer_load_dword [[REGA:v[0-9]+]]
|
||||
; SI: buffer_load_dword [[REGB:v[0-9]+]]
|
||||
; SI: buffer_load_dword [[REGC:v[0-9]+]]
|
||||
; SI: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], |[[REGB]]|, -[[REGC]]
|
||||
; GCN-LABEL: {{^}}mad_fabs_sub_f32:
|
||||
; GCN: {{buffer|flat}}_load_dword [[REGA:v[0-9]+]]
|
||||
; GCN: {{buffer|flat}}_load_dword [[REGB:v[0-9]+]]
|
||||
; GCN: {{buffer|flat}}_load_dword [[REGC:v[0-9]+]]
|
||||
; GCN: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], |[[REGB]]|, -[[REGC]]
|
||||
; SI: buffer_store_dword [[RESULT]]
|
||||
; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
|
||||
define void @mad_fabs_sub_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 {
|
||||
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
@ -169,12 +177,14 @@ define void @mad_fabs_sub_f32(float addrspace(1)* noalias nocapture %out, float
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}fsub_c_fadd_a_a:
|
||||
; SI-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI: v_mac_f32_e32 [[R2]], -2.0, [[R1]]
|
||||
; GCN-LABEL: {{^}}fsub_c_fadd_a_a_f32:
|
||||
; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
|
||||
; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
|
||||
; GCN: v_mac_f32_e32 [[R2]], -2.0, [[R1]]
|
||||
|
||||
; SI: buffer_store_dword [[R2]]
|
||||
define void @fsub_c_fadd_a_a(float addrspace(1)* %out, float addrspace(1)* %in) {
|
||||
; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
|
||||
define void @fsub_c_fadd_a_a_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
||||
%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
|
||||
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
|
||||
@ -190,12 +200,14 @@ define void @fsub_c_fadd_a_a(float addrspace(1)* %out, float addrspace(1)* %in)
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}fsub_fadd_a_a_c:
|
||||
; SI-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], -[[R2]]
|
||||
; GCN-LABEL: {{^}}fsub_fadd_a_a_c_f32:
|
||||
; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
|
||||
; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
|
||||
; GCN: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], -[[R2]]
|
||||
|
||||
; SI: buffer_store_dword [[RESULT]]
|
||||
define void @fsub_fadd_a_a_c(float addrspace(1)* %out, float addrspace(1)* %in) {
|
||||
; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
|
||||
define void @fsub_fadd_a_a_c_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
||||
%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
|
||||
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user