RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-12-04 01:43:06 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Minor code reorganization.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55071 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-08-20 18:10:48 +00:00
parent 77ad79689d
commit 4cbe0662ab
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/CodeGen/SelectionDAG/FastISel.cpp
View File

@ -146,8 +146,8 @@ unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
const TargetRegisterClass* RC) { const TargetRegisterClass* RC) {
MachineRegisterInfo &MRI = MF->getRegInfo(); MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetInstrDesc &II = TII->get(MachineInstOpcode);
unsigned ResultReg = MRI.createVirtualRegister(RC); unsigned ResultReg = MRI.createVirtualRegister(RC);
const TargetInstrDesc &II = TII->get(MachineInstOpcode);
MachineInstr *MI = BuildMI(*MF, II, ResultReg); MachineInstr *MI = BuildMI(*MF, II, ResultReg);
@ -159,8 +159,8 @@ unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
unsigned Op0) { unsigned Op0) {
MachineRegisterInfo &MRI = MF->getRegInfo(); MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetInstrDesc &II = TII->get(MachineInstOpcode);
unsigned ResultReg = MRI.createVirtualRegister(RC); unsigned ResultReg = MRI.createVirtualRegister(RC);
const TargetInstrDesc &II = TII->get(MachineInstOpcode);
MachineInstr *MI = BuildMI(*MF, II, ResultReg); MachineInstr *MI = BuildMI(*MF, II, ResultReg);
MI->addOperand(MachineOperand::CreateReg(Op0, false)); MI->addOperand(MachineOperand::CreateReg(Op0, false));
@ -173,8 +173,8 @@ unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
unsigned Op0, unsigned Op1) { unsigned Op0, unsigned Op1) {
MachineRegisterInfo &MRI = MF->getRegInfo(); MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetInstrDesc &II = TII->get(MachineInstOpcode);
unsigned ResultReg = MRI.createVirtualRegister(RC); unsigned ResultReg = MRI.createVirtualRegister(RC);
const TargetInstrDesc &II = TII->get(MachineInstOpcode);
MachineInstr *MI = BuildMI(*MF, II, ResultReg); MachineInstr *MI = BuildMI(*MF, II, ResultReg);
MI->addOperand(MachineOperand::CreateReg(Op0, false)); MI->addOperand(MachineOperand::CreateReg(Op0, false));