RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-11-25 20:59:51 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Add definition of WSBH (Word Swap Bytes within Halfwords), which is an

Browse Source 
instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
 
WSBW is removed since it is not an instruction the current architectures
support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147015 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-12-20 23:47:44 +00:00
parent e1bcd6b5c6
commit 4d2b0f3ce7
2 changed files with 10 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/Mips/Mips.td
View File

@ -63,7 +63,7 @@ def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
[FeatureCondMov, FeatureBitCount]>;
def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
"Mips32r2", "Mips32r2 ISA Support",
[FeatureMips32, FeatureSEInReg]>;
[FeatureMips32, FeatureSEInReg, FeatureSwap]>;
def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
"Mips64", "Mips64 ISA Support",
[FeatureGP64Bit, FeatureFP64Bit,

16
lib/Target/Mips/MipsInstrInfo.td
View File

@ -625,11 +625,10 @@ class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt>:
let Predicates = [HasSEInReg];
}
// Byte Swap
class ByteSwap<bits<6> func, bits<5> sa, string instr_asm>:
FR<0x1f, func, (outs CPURegs:$rd), (ins CPURegs:$rt),
!strconcat(instr_asm, "\t$rd, $rt"),
[(set CPURegs:$rd, (bswap CPURegs:$rt))], NoItinerary> {
// Subword Swap
class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>:
FR<0x1f, func, (outs RC:$rd), (ins RC:$rt),
!strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> {
let rs = 0;
let shamt = sa;
let Predicates = [HasSwap];
@ -895,8 +894,8 @@ def SEH : SignExtInReg<0x18, "seh", i16>;
def CLZ : CountLeading0<0x20, "clz", CPURegs>;
def CLO : CountLeading1<0x21, "clo", CPURegs>;
/// Byte Swap
def WSBW : ByteSwap<0x20, 0x2, "wsbw">;
/// Word Swap Bytes Within Halfwords
def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>;
/// No operation
let addr=0 in
@ -1104,6 +1103,9 @@ defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
// select MipsDynAlloc
def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
// bswap pattern
def : Pat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
//===----------------------------------------------------------------------===//
// Floating Point Support
//===----------------------------------------------------------------------===//