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AVX-512: Added CMP and BLEND instructions.
Lowering for SETCC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188265 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
bd980e5569
commit
4d36bd80e6
@ -9705,6 +9705,42 @@ static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
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DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
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}
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static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
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SDValue Cond;
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SDValue Op0 = Op.getOperand(0);
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SDValue Op1 = Op.getOperand(1);
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SDValue CC = Op.getOperand(2);
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MVT VT = Op.getValueType().getSimpleVT();
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EVT OpVT = Op0.getValueType();
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assert(OpVT.getVectorElementType().getSizeInBits() >= 32 &&
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Op.getValueType().getScalarType() == MVT::i1 &&
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"Cannot set masked compare for this operation");
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ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
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SDLoc dl(Op);
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bool Unsigned = false;
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unsigned SSECC;
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switch (SetCCOpcode) {
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default: llvm_unreachable("Unexpected SETCC condition");
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case ISD::SETNE: SSECC = 4; break;
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case ISD::SETEQ: SSECC = 0; break;
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case ISD::SETUGT: Unsigned = true;
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case ISD::SETGT: SSECC = 6; break; // NLE
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case ISD::SETULT: Unsigned = true;
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case ISD::SETLT: SSECC = 1; break;
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case ISD::SETUGE: Unsigned = true;
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case ISD::SETGE: SSECC = 5; break; // NLT
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case ISD::SETULE: Unsigned = true;
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case ISD::SETLE: SSECC = 2; break;
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}
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unsigned Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
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return DAG.getNode(Opc, dl, VT, Op0, Op1,
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DAG.getConstant(SSECC, MVT::i8));
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}
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static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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SDValue Cond;
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@ -9723,7 +9759,12 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
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#endif
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unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
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unsigned Opc = X86ISD::CMPP;
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unsigned NumElems = VT.getVectorNumElements();
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if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
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assert(NumElems <=16);
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Opc = X86ISD::CMPM;
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}
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// In the two special cases we can't handle, emit two comparisons.
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if (SSECC == 8) {
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unsigned CC0, CC1;
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@ -9735,14 +9776,14 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
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CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
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}
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SDValue Cmp0 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
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SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
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DAG.getConstant(CC0, MVT::i8));
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SDValue Cmp1 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
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SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
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DAG.getConstant(CC1, MVT::i8));
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return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
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}
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// Handle all other FP comparisons here.
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return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
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return DAG.getNode(Opc, dl, VT, Op0, Op1,
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DAG.getConstant(SSECC, MVT::i8));
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}
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@ -9750,6 +9791,24 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
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if (VT.is256BitVector() && !Subtarget->hasInt256())
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return Lower256IntVSETCC(Op, DAG);
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bool MaskResult = (VT.getVectorElementType() == MVT::i1);
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EVT OpVT = Op1.getValueType();
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if (Subtarget->hasAVX512()) {
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if (Op1.getValueType().is512BitVector() ||
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(MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
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return LowerIntVSETCC_AVX512(Op, DAG);
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// In AVX-512 architecture setcc returns mask with i1 elements,
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// But there is no compare instruction for i8 and i16 elements.
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// We are not talking about 512-bit operands in this case, these
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// types are illegal.
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if (MaskResult &&
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(OpVT.getVectorElementType().getSizeInBits() < 32 &&
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OpVT.getVectorElementType().getSizeInBits() >= 8))
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return DAG.getNode(ISD::TRUNCATE, dl, VT,
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DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
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}
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// We are handling one of the integer comparisons here. Since SSE only has
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// GT and EQ comparisons for integer, swapping operands and multiple
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// operations may be required for some comparisons.
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@ -9759,15 +9818,18 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
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switch (SetCCOpcode) {
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default: llvm_unreachable("Unexpected SETCC condition");
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case ISD::SETNE: Invert = true;
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case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
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case ISD::SETEQ: Opc = MaskResult? X86ISD::PCMPEQM: X86ISD::PCMPEQ; break;
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case ISD::SETLT: Swap = true;
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case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
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case ISD::SETGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; break;
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case ISD::SETGE: Swap = true;
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case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
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case ISD::SETLE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
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Invert = true; break;
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case ISD::SETULT: Swap = true;
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case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
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case ISD::SETUGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
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FlipSigns = true; break;
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case ISD::SETUGE: Swap = true;
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case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
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case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
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FlipSigns = true; Invert = true; break;
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}
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// Special case: Use min/max operations for SETULE/SETUGE
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@ -13201,6 +13263,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::CMP: return "X86ISD::CMP";
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case X86ISD::COMI: return "X86ISD::COMI";
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case X86ISD::UCOMI: return "X86ISD::UCOMI";
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case X86ISD::CMPM: return "X86ISD::CMPM";
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case X86ISD::CMPMU: return "X86ISD::CMPMU";
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case X86ISD::SETCC: return "X86ISD::SETCC";
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case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
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case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
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@ -13273,6 +13337,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::CMPP: return "X86ISD::CMPP";
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case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
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case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
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case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
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case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
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case X86ISD::ADD: return "X86ISD::ADD";
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case X86ISD::SUB: return "X86ISD::SUB";
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case X86ISD::ADC: return "X86ISD::ADC";
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@ -274,6 +274,13 @@ namespace llvm {
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// PCMP* - Vector integer comparisons.
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PCMPEQ, PCMPGT,
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// PCMP*M - Vector integer comparisons, the result is in a mask vector
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PCMPEQM, PCMPGTM,
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/// CMPM, CMPMU - Vector comparison generating mask bits for fp and
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/// integer signed and unsigned data types.
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CMPM,
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CMPMU,
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// ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
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ADD, SUB, ADC, SBB, SMUL,
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@ -564,7 +564,195 @@ defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512me
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defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
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v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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//===----------------------------------------------------------------------===//
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// AVX-512 - BLEND using mask
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//
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multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
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RegisterClass KRC, RegisterClass RC,
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X86MemOperand x86memop, PatFrag mem_frag,
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SDNode OpNode, ValueType vt> {
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def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
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(ins KRC:$mask, RC:$src1, RC:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, ${dst}{${mask}}|${dst}{${mask}}, $src1, $src2}"),
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[(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
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(vt RC:$src1)))]>, EVEX_4V, EVEX_K;
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def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
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(ins KRC:$mask, RC:$src1, x86memop:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $mask, $dst|$dst, $mask, $src1, $src2}"),
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[]>,
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EVEX_4V, EVEX_K;
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}
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let ExeDomain = SSEPackedSingle in
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defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps", VK16WM, VR512, f512mem,
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memopv16f32, vselect, v16f32>,
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EVEX_CD8<32, CD8VF>, EVEX_V512;
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let ExeDomain = SSEPackedDouble in
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defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd", VK8WM, VR512, f512mem,
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memopv8f64, vselect, v8f64>,
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VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
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defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd", VK16WM, VR512, f512mem,
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memopv8i64, vselect, v16i32>,
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EVEX_CD8<32, CD8VF>, EVEX_V512;
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defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq", VK8WM, VR512, f512mem,
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memopv8i64, vselect, v8i64>, VEX_W,
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EVEX_CD8<64, CD8VF>, EVEX_V512;
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let Predicates = [HasAVX512] in {
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def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
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(v8f32 VR256X:$src2))),
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(EXTRACT_SUBREG
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(v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
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(v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
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(v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
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def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
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(v8i32 VR256X:$src2))),
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(EXTRACT_SUBREG
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(v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
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(v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
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(v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
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}
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multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
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RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
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SDNode OpNode, ValueType vt> {
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def rr : AVX512BI<opc, MRMSrcReg,
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(outs KRC:$dst), (ins RC:$src1, RC:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
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IIC_SSE_CMPP_RR>, EVEX_4V;
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def rm : AVX512BI<opc, MRMSrcMem,
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(outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set KRC:$dst, (OpNode (vt RC:$src1),
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(bitconvert (memop_frag addr:$src2))))],
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IIC_SSE_CMPP_RM>, EVEX_4V;
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}
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defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
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memopv8i64, X86pcmpeqm, v16i32>, EVEX_V512;
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defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
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memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
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defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
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memopv8i64, X86pcmpgtm, v16i32>, EVEX_V512;
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defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
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memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
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def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
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(COPY_TO_REGCLASS (VPCMPGTDZrr
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(v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
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(v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
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def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
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(COPY_TO_REGCLASS (VPCMPEQDZrr
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(v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
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(v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
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multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
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RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
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SDNode OpNode, ValueType vt, Operand CC, string asm,
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string asm_alt> {
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def rri : AVX512AIi8<opc, MRMSrcReg,
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(outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
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[(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
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IIC_SSE_CMPP_RR>, EVEX_4V;
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def rmi : AVX512AIi8<opc, MRMSrcMem,
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(outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
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[(set KRC:$dst, (OpNode (vt RC:$src1),
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(bitconvert (memop_frag addr:$src2)), imm:$cc))],
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IIC_SSE_CMPP_RM>, EVEX_4V;
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// Accept explicit immediate argument form instead of comparison code.
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let neverHasSideEffects = 1 in {
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def rri_alt : AVX512AIi8<opc, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
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asm_alt, [], IIC_SSE_CMPP_RR>, EVEX_4V;
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def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
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asm_alt, [], IIC_SSE_CMPP_RM>, EVEX_4V;
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}
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}
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defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv8i64,
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X86cmpm, v16i32, AVXCC,
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"vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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"vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv8i64,
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X86cmpmu, v16i32, AVXCC,
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"vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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"vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
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X86cmpm, v8i64, AVXCC,
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"vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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"vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
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VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
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defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
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X86cmpmu, v8i64, AVXCC,
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"vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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"vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
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VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
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// avx512_cmp_packed - sse 1 & 2 compare packed instructions
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multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
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X86MemOperand x86memop, Operand CC,
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SDNode OpNode, ValueType vt, string asm,
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string asm_alt, Domain d> {
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def rri : AVX512PIi8<0xC2, MRMSrcReg,
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(outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
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[(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
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def rmi : AVX512PIi8<0xC2, MRMSrcMem,
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(outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
|
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[(set KRC:$dst,
|
||||
(OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
|
||||
|
||||
// Accept explicit immediate argument form instead of comparison code.
|
||||
let neverHasSideEffects = 1 in {
|
||||
def rri_alt : PIi8<0xC2, MRMSrcReg,
|
||||
(outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
|
||||
asm_alt, [], IIC_SSE_CMPP_RR, d>;
|
||||
def rmi_alt : PIi8<0xC2, MRMSrcMem,
|
||||
(outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
|
||||
asm_alt, [], IIC_SSE_CMPP_RM, d>;
|
||||
}
|
||||
}
|
||||
|
||||
defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
|
||||
"vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
"vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
|
||||
SSEPackedSingle>, TB, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
|
||||
defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
|
||||
"vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
"vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
|
||||
SSEPackedDouble>, TB, OpSize, EVEX_4V, VEX_W, EVEX_V512,
|
||||
EVEX_CD8<64, CD8VF>;
|
||||
|
||||
def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
|
||||
(COPY_TO_REGCLASS (VCMPPSZrri
|
||||
(v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
|
||||
(v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
|
||||
imm:$cc), VK8)>;
|
||||
def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
|
||||
(COPY_TO_REGCLASS (VPCMPDZrri
|
||||
(v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
|
||||
(v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
|
||||
imm:$cc), VK8)>;
|
||||
def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
|
||||
(COPY_TO_REGCLASS (VPCMPUDZrri
|
||||
(v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
|
||||
(v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
|
||||
imm:$cc), VK8)>;
|
||||
|
||||
// Mask register copy, including
|
||||
// - copy between mask registers
|
||||
// - load/store mask registers
|
||||
@ -949,4 +1137,18 @@ defm VMOVDQU32 : avx512_mov_int<0x6F, "vmovdqu32", VR512, VK16WM, memopv16i32, i
|
||||
defm VMOVDQU64 : avx512_mov_int<0x6F, "vmovdqu64", VR512, VK8WM, memopv8i64, i512mem>,
|
||||
EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
|
||||
|
||||
let AddedComplexity = 20 in {
|
||||
def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
|
||||
(v16f32 VR512:$src2))),
|
||||
(VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
|
||||
def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
|
||||
(v8f64 VR512:$src2))),
|
||||
(VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
|
||||
def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
|
||||
(v16i32 VR512:$src2))),
|
||||
(VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
|
||||
def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
|
||||
(v8i64 VR512:$src2))),
|
||||
(VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
|
||||
}
|
||||
|
||||
|
||||
@ -118,6 +118,15 @@ def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
|
||||
def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
|
||||
def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
|
||||
|
||||
def X86IntCmpMask : SDTypeProfile<1, 2,
|
||||
[SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
|
||||
def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
|
||||
def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
|
||||
|
||||
def X86CmpMaskCC : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
|
||||
def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
|
||||
def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
|
||||
|
||||
def X86vshl : SDNode<"X86ISD::VSHL",
|
||||
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
||||
SDTCisVec<2>]>>;
|
||||
|
||||
113
test/CodeGen/X86/avx512-vec-cmp.ll
Normal file
113
test/CodeGen/X86/avx512-vec-cmp.ll
Normal file
@ -0,0 +1,113 @@
|
||||
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: test1
|
||||
; CHECK: vcmpleps
|
||||
; CHECK: vmovups
|
||||
; CHECK: ret
|
||||
define <16 x float> @test1(<16 x float> %x, <16 x float> %y) nounwind {
|
||||
%mask = fcmp ole <16 x float> %x, %y
|
||||
%max = select <16 x i1> %mask, <16 x float> %x, <16 x float> %y
|
||||
ret <16 x float> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test2
|
||||
; CHECK: vcmplepd
|
||||
; CHECK: vmovupd
|
||||
; CHECK: ret
|
||||
define <8 x double> @test2(<8 x double> %x, <8 x double> %y) nounwind {
|
||||
%mask = fcmp ole <8 x double> %x, %y
|
||||
%max = select <8 x i1> %mask, <8 x double> %x, <8 x double> %y
|
||||
ret <8 x double> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test3
|
||||
; CHECK: vpcmpeqd
|
||||
; CHECK: vmovdqu32
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test3(<16 x i32> %x, <16 x i32> %y) nounwind {
|
||||
%mask = icmp eq <16 x i32> %x, %y
|
||||
%max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %y
|
||||
ret <16 x i32> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @test4_unsigned
|
||||
; CHECK: vpcmpnltud
|
||||
; CHECK: vmovdqu32
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test4_unsigned(<16 x i32> %x, <16 x i32> %y) nounwind {
|
||||
%mask = icmp uge <16 x i32> %x, %y
|
||||
%max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %y
|
||||
ret <16 x i32> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test5
|
||||
; CHECK: vpcmpeqq {{.*}}%k1
|
||||
; CHECK: vmovdqu64 {{.*}}%k1
|
||||
; CHECK: ret
|
||||
define <8 x i64> @test5(<8 x i64> %x, <8 x i64> %y) nounwind {
|
||||
%mask = icmp eq <8 x i64> %x, %y
|
||||
%max = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> %y
|
||||
ret <8 x i64> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test6_unsigned
|
||||
; CHECK: vpcmpnleuq {{.*}}%k1
|
||||
; CHECK: vmovdqu64 {{.*}}%k1
|
||||
; CHECK: ret
|
||||
define <8 x i64> @test6_unsigned(<8 x i64> %x, <8 x i64> %y) nounwind {
|
||||
%mask = icmp ugt <8 x i64> %x, %y
|
||||
%max = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> %y
|
||||
ret <8 x i64> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test7
|
||||
; CHECK: xor
|
||||
; CHECK: vcmpltps
|
||||
; CHECK: vblendvps
|
||||
; CHECK: ret
|
||||
define <4 x float> @test7(<4 x float> %a, <4 x float> %b) {
|
||||
%mask = fcmp olt <4 x float> %a, zeroinitializer
|
||||
%c = select <4 x i1>%mask, <4 x float>%a, <4 x float>%b
|
||||
ret <4 x float>%c
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test8
|
||||
; CHECK: xor
|
||||
; CHECK: vcmpltpd
|
||||
; CHECK: vblendvpd
|
||||
; CHECK: ret
|
||||
define <2 x double> @test8(<2 x double> %a, <2 x double> %b) {
|
||||
%mask = fcmp olt <2 x double> %a, zeroinitializer
|
||||
%c = select <2 x i1>%mask, <2 x double>%a, <2 x double>%b
|
||||
ret <2 x double>%c
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test9
|
||||
; CHECK: vpcmpeqd
|
||||
; CHECK: vpblendmd
|
||||
; CHECK: ret
|
||||
define <8 x i32> @test9(<8 x i32> %x, <8 x i32> %y) nounwind {
|
||||
%mask = icmp eq <8 x i32> %x, %y
|
||||
%max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %y
|
||||
ret <8 x i32> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test10
|
||||
; CHECK: vcmpeqps
|
||||
; CHECK: vblendmps
|
||||
; CHECK: ret
|
||||
define <8 x float> @test10(<8 x float> %x, <8 x float> %y) nounwind {
|
||||
%mask = fcmp oeq <8 x float> %x, %y
|
||||
%max = select <8 x i1> %mask, <8 x float> %x, <8 x float> %y
|
||||
ret <8 x float> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test11_unsigned
|
||||
; CHECK: vpcmpnleud %zmm
|
||||
; CHECK: vpblendmd %zmm
|
||||
; CHECK: ret
|
||||
define <8 x i32> @test11_unsigned(<8 x i32> %x, <8 x i32> %y) nounwind {
|
||||
%mask = icmp ugt <8 x i32> %x, %y
|
||||
%max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %y
|
||||
ret <8 x i32> %max
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user