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AArch64: stop trying to use 32-bit MOVZs when expanding patchpoints.
Of course the assembly was right but because the opcode was MOVZWi it was encoded as "movz w16, #65535, lsl #32" which is an unallocated encoding and would go horribly wrong on a CPU. No idea how this bug survived this long. It seems nobody is using that aspect of patchpoints. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272831 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -404,16 +404,16 @@ void AArch64AsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
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unsigned ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
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EncodedBytes = 16;
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// Materialize the jump address:
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EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVZWi)
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EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVZXi)
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.addReg(ScratchReg)
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.addImm((CallTarget >> 32) & 0xFFFF)
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.addImm(32));
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EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKWi)
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EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi)
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.addReg(ScratchReg)
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.addReg(ScratchReg)
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.addImm((CallTarget >> 16) & 0xFFFF)
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.addImm(16));
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EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKWi)
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EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi)
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.addReg(ScratchReg)
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.addReg(ScratchReg)
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.addImm(CallTarget & 0xFFFF)
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@ -1,5 +1,12 @@
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; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone < %s | FileCheck %s
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; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone < %s | FileCheck %s
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; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone -fast-isel < %s | FileCheck %s --check-prefix=FAST
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; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone -filetype=obj -o %t %s
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; RUN: llvm-objdump -triple arm64-apple-darwin -d %t | FileCheck %s --check-prefix CHECK-ENCODING
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; CHECK-ENCODING-NOT: <unknown>
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; CHECK-ENCODING: movz x16, #65535, lsl #32
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; CHECK-ENCODING: movk x16, #57005, lsl #16
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; CHECK-ENCODING: movk x16, #48879
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; One argument will be passed in register, the other will be pushed on the stack.
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; Return value in x0.
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@ -11,8 +18,8 @@ entry:
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; CHECK-NEXT: mov x0, x{{.+}}
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; CHECK: Ltmp
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; CHECK-NEXT: movz x16, #65535, lsl #32
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; CHECK-NEXT: movk x16, #57005, lsl #16
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; CHECK-NEXT: movk x16, #48879
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; CHECK: movk x16, #57005, lsl #16
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; CHECK: movk x16, #48879
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; CHECK-NEXT: blr x16
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; FAST-LABEL: jscall_patchpoint_codegen:
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; FAST: Ltmp
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