mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-17 00:46:42 +00:00
reduce indentation, fit in 80 cols and various other cosmetic cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99989 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
b6c72b92c2
commit
4dd8163091
@ -118,8 +118,8 @@ namespace {
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bool isVirtRegModified(unsigned Reg) const {
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assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
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assert(Reg - TargetRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
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&& "Illegal virtual register!");
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assert(Reg - TargetRegisterInfo::FirstVirtualRegister <
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VirtRegModified.size() && "Illegal virtual register!");
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return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister];
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}
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@ -135,15 +135,16 @@ namespace {
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if (PhysRegsUseOrder.empty() ||
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PhysRegsUseOrder.back() == Reg) return; // Already most recently used
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for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i)
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if (areRegsEqual(Reg, PhysRegsUseOrder[i-1])) {
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unsigned RegMatch = PhysRegsUseOrder[i-1]; // remove from middle
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PhysRegsUseOrder.erase(PhysRegsUseOrder.begin()+i-1);
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// Add it to the end of the list
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PhysRegsUseOrder.push_back(RegMatch);
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if (RegMatch == Reg)
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return; // Found an exact match, exit early
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}
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for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i) {
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unsigned RegMatch = PhysRegsUseOrder[i-1]; // remove from middle
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if (!areRegsEqual(Reg, RegMatch)) continue;
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PhysRegsUseOrder.erase(PhysRegsUseOrder.begin()+i-1);
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// Add it to the end of the list
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PhysRegsUseOrder.push_back(RegMatch);
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if (RegMatch == Reg)
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return; // Found an exact match, exit early
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}
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}
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public:
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@ -267,7 +268,7 @@ int RALocal::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
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int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
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RC->getAlignment());
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// Assign the slot...
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// Assign the slot.
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StackSlotForVirtReg[VirtReg] = FrameIdx;
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return FrameIdx;
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}
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@ -337,15 +338,19 @@ void RALocal::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
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assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!");
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if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs)
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spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg);
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} else {
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// If the selected register aliases any other registers, we must make
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// sure that one of the aliases isn't alive.
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for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
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*AliasSet; ++AliasSet)
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if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register.
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PhysRegsUsed[*AliasSet] != -2) // If allocatable.
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if (PhysRegsUsed[*AliasSet])
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spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
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return;
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}
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// If the selected register aliases any other registers, we must make
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// sure that one of the aliases isn't alive.
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for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
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*AliasSet; ++AliasSet) {
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if (PhysRegsUsed[*AliasSet] == -1 || // Spill aliased register.
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PhysRegsUsed[*AliasSet] == -2) // If allocatable.
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continue;
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if (PhysRegsUsed[*AliasSet])
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spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
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}
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}
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@ -410,59 +415,64 @@ unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I,
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// First check to see if we have a free register of the requested type...
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unsigned PhysReg = NoFree ? 0 : getFreeReg(RC);
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if (PhysReg != 0) {
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// Assign the register.
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assignVirtToPhysReg(VirtReg, PhysReg);
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return PhysReg;
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}
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// If we didn't find an unused register, scavenge one now!
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if (PhysReg == 0) {
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assert(!PhysRegsUseOrder.empty() && "No allocated registers??");
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assert(!PhysRegsUseOrder.empty() && "No allocated registers??");
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// Loop over all of the preallocated registers from the least recently used
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// to the most recently used. When we find one that is capable of holding
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// our register, use it.
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for (unsigned i = 0; PhysReg == 0; ++i) {
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assert(i != PhysRegsUseOrder.size() &&
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"Couldn't find a register of the appropriate class!");
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// Loop over all of the preallocated registers from the least recently used
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// to the most recently used. When we find one that is capable of holding
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// our register, use it.
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for (unsigned i = 0; PhysReg == 0; ++i) {
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assert(i != PhysRegsUseOrder.size() &&
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"Couldn't find a register of the appropriate class!");
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unsigned R = PhysRegsUseOrder[i];
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unsigned R = PhysRegsUseOrder[i];
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// We can only use this register if it holds a virtual register (ie, it
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// can be spilled). Do not use it if it is an explicitly allocated
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// physical register!
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assert(PhysRegsUsed[R] != -1 &&
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"PhysReg in PhysRegsUseOrder, but is not allocated?");
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if (PhysRegsUsed[R] && PhysRegsUsed[R] != -2) {
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// If the current register is compatible, use it.
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if (RC->contains(R)) {
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PhysReg = R;
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break;
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} else {
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// If one of the registers aliased to the current register is
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// compatible, use it.
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for (const unsigned *AliasIt = TRI->getAliasSet(R);
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*AliasIt; ++AliasIt) {
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if (RC->contains(*AliasIt) &&
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// If this is pinned down for some reason, don't use it. For
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// example, if CL is pinned, and we run across CH, don't use
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// CH as justification for using scavenging ECX (which will
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// fail).
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PhysRegsUsed[*AliasIt] != 0 &&
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// Make sure the register is allocatable. Don't allocate SIL on
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// x86-32.
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PhysRegsUsed[*AliasIt] != -2) {
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PhysReg = *AliasIt; // Take an aliased register
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break;
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}
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}
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}
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// We can only use this register if it holds a virtual register (ie, it
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// can be spilled). Do not use it if it is an explicitly allocated
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// physical register!
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assert(PhysRegsUsed[R] != -1 &&
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"PhysReg in PhysRegsUseOrder, but is not allocated?");
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if (PhysRegsUsed[R] && PhysRegsUsed[R] != -2) {
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// If the current register is compatible, use it.
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if (RC->contains(R)) {
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PhysReg = R;
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break;
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}
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// If one of the registers aliased to the current register is
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// compatible, use it.
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for (const unsigned *AliasIt = TRI->getAliasSet(R);
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*AliasIt; ++AliasIt) {
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if (!RC->contains(*AliasIt)) continue;
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// If this is pinned down for some reason, don't use it. For
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// example, if CL is pinned, and we run across CH, don't use
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// CH as justification for using scavenging ECX (which will
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// fail).
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if (PhysRegsUsed[*AliasIt] == 0) continue;
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// Make sure the register is allocatable. Don't allocate SIL on
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// x86-32.
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if (PhysRegsUsed[*AliasIt] == -2) continue;
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PhysReg = *AliasIt; // Take an aliased register
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break;
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}
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}
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assert(PhysReg && "Physical register not assigned!?!?");
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// At this point PhysRegsUseOrder[i] is the least recently used register of
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// compatible register class. Spill it to memory and reap its remains.
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spillPhysReg(MBB, I, PhysReg);
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}
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assert(PhysReg && "Physical register not assigned!?!?");
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// At this point PhysRegsUseOrder[i] is the least recently used register of
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// compatible register class. Spill it to memory and reap its remains.
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spillPhysReg(MBB, I, PhysReg);
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// Now that we know which register we need to assign this to, do it now!
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assignVirtToPhysReg(VirtReg, PhysReg);
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return PhysReg;
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@ -543,17 +553,17 @@ MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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}
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for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
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*SubRegs; ++SubRegs) {
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if (!ReloadedRegs.insert(*SubRegs)) {
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std::string msg;
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raw_string_ostream Msg(msg);
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Msg << "Ran out of registers during register allocation!";
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if (MI->isInlineAsm()) {
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Msg << "\nPlease check your inline asm statement for invalid "
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<< "constraints:\n";
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MI->print(Msg, TM);
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}
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llvm_report_error(Msg.str());
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if (ReloadedRegs.insert(*SubRegs)) continue;
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std::string msg;
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raw_string_ostream Msg(msg);
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Msg << "Ran out of registers during register allocation!";
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if (MI->isInlineAsm()) {
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Msg << "\nPlease check your inline asm statement for invalid "
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<< "constraints:\n";
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MI->print(Msg, TM);
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}
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llvm_report_error(Msg.str());
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}
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return MI;
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@ -563,7 +573,7 @@ MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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/// read/mod/write register, i.e. update partial register.
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static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand& MO = MI->getOperand(i);
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
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MO.isDef() && !MO.isDead())
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return true;
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@ -575,7 +585,7 @@ static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
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/// read/mod/write register, i.e. update partial register.
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static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand& MO = MI->getOperand(i);
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
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!MO.isDef() && MO.isKill())
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return true;
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@ -606,7 +616,7 @@ static bool precedes(MachineBasicBlock::iterator A,
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/// ComputeLocalLiveness - Computes liveness of registers within a basic
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/// block, setting the killed/dead flags as appropriate.
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void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) {
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MachineRegisterInfo& MRI = MBB.getParent()->getRegInfo();
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MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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// Keep track of the most recently seen previous use or def of each reg,
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// so that we can update them with dead/kill markers.
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DenseMap<unsigned, std::pair<MachineInstr*, unsigned> > LastUseDef;
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@ -614,58 +624,60 @@ void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) {
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I != E; ++I) {
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if (I->isDebugValue())
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continue;
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for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
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MachineOperand& MO = I->getOperand(i);
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MachineOperand &MO = I->getOperand(i);
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// Uses don't trigger any flags, but we need to save
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// them for later. Also, we have to process these
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// _before_ processing the defs, since an instr
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// uses regs before it defs them.
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if (MO.isReg() && MO.getReg() && MO.isUse()) {
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LastUseDef[MO.getReg()] = std::make_pair(I, i);
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if (!MO.isReg() || !MO.getReg() || !MO.isUse())
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continue;
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LastUseDef[MO.getReg()] = std::make_pair(I, i);
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if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) continue;
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const unsigned *Aliases = TRI->getAliasSet(MO.getReg());
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if (Aliases == 0)
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continue;
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while (*Aliases) {
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DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
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alias = LastUseDef.find(*Aliases);
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if (alias != LastUseDef.end() && alias->second.first != I)
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LastUseDef[*Aliases] = std::make_pair(I, i);
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if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) continue;
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const unsigned* Aliases = TRI->getAliasSet(MO.getReg());
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if (Aliases) {
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while (*Aliases) {
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DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
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alias = LastUseDef.find(*Aliases);
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if (alias != LastUseDef.end() && alias->second.first != I)
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LastUseDef[*Aliases] = std::make_pair(I, i);
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++Aliases;
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}
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}
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++Aliases;
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}
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}
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for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
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MachineOperand& MO = I->getOperand(i);
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MachineOperand &MO = I->getOperand(i);
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// Defs others than 2-addr redefs _do_ trigger flag changes:
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// - A def followed by a def is dead
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// - A use followed by a def is a kill
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if (MO.isReg() && MO.getReg() && MO.isDef()) {
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DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
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last = LastUseDef.find(MO.getReg());
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if (last != LastUseDef.end()) {
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// Check if this is a two address instruction. If so, then
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// the def does not kill the use.
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if (last->second.first == I &&
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I->isRegTiedToUseOperand(i))
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continue;
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MachineOperand& lastUD =
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last->second.first->getOperand(last->second.second);
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if (lastUD.isDef())
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lastUD.setIsDead(true);
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else
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lastUD.setIsKill(true);
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}
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if (!MO.isReg() || !MO.getReg() || !MO.isDef()) continue;
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DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
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last = LastUseDef.find(MO.getReg());
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if (last != LastUseDef.end()) {
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// Check if this is a two address instruction. If so, then
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// the def does not kill the use.
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if (last->second.first == I &&
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I->isRegTiedToUseOperand(i))
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continue;
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LastUseDef[MO.getReg()] = std::make_pair(I, i);
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MachineOperand &lastUD =
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last->second.first->getOperand(last->second.second);
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if (lastUD.isDef())
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lastUD.setIsDead(true);
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else
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lastUD.setIsKill(true);
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}
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LastUseDef[MO.getReg()] = std::make_pair(I, i);
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}
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}
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@ -687,9 +699,9 @@ void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) {
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// in the block and determine if it is dead.
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for (DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
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I = LastUseDef.begin(), E = LastUseDef.end(); I != E; ++I) {
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MachineInstr* MI = I->second.first;
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MachineInstr *MI = I->second.first;
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unsigned idx = I->second.second;
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MachineOperand& MO = MI->getOperand(idx);
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MachineOperand &MO = MI->getOperand(idx);
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bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(MO.getReg());
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@ -712,20 +724,21 @@ void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) {
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// Two cases:
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// - used in another block
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// - used in the same block before it is defined (loop)
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if (UI->getParent() != &MBB ||
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(MO.isDef() && UI.getOperand().isUse() && precedes(&*UI, MI))) {
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if (UI->isDebugValue()) {
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UsedByDebugValueOnly = true;
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continue;
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}
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// A non-DBG_VALUE use means we can leave DBG_VALUE uses alone.
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UsedInMultipleBlocks.set(MO.getReg() -
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TargetRegisterInfo::FirstVirtualRegister);
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usedOutsideBlock = true;
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UsedByDebugValueOnly = false;
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break;
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if (UI->getParent() == &MBB &&
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!(MO.isDef() && UI.getOperand().isUse() && precedes(&*UI, MI)))
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continue;
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if (UI->isDebugValue()) {
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UsedByDebugValueOnly = true;
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continue;
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}
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// A non-DBG_VALUE use means we can leave DBG_VALUE uses alone.
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UsedInMultipleBlocks.set(MO.getReg() -
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TargetRegisterInfo::FirstVirtualRegister);
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usedOutsideBlock = true;
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UsedByDebugValueOnly = false;
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break;
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}
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if (UsedByDebugValueOnly)
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@ -770,11 +783,11 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
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AddToPhysRegsUseOrder(Reg);
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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*SubRegs; ++SubRegs) {
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if (PhysRegsUsed[*SubRegs] != -2) {
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AddToPhysRegsUseOrder(*SubRegs);
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PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
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MF->getRegInfo().setPhysRegUsed(*SubRegs);
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}
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if (PhysRegsUsed[*SubRegs] == -2) continue;
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AddToPhysRegsUseOrder(*SubRegs);
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PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
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MF->getRegInfo().setPhysRegUsed(*SubRegs);
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}
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}
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@ -813,16 +826,16 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
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SmallVector<unsigned, 8> Kills;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand& MO = MI->getOperand(i);
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if (MO.isReg() && MO.isKill()) {
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if (!MO.isImplicit())
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Kills.push_back(MO.getReg());
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else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
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// These are extra physical register kills when a sub-register
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// is defined (def of a sub-register is a read/mod/write of the
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// larger registers). Ignore.
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Kills.push_back(MO.getReg());
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}
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isKill()) continue;
|
||||
|
||||
if (!MO.isImplicit())
|
||||
Kills.push_back(MO.getReg());
|
||||
else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
|
||||
// These are extra physical register kills when a sub-register
|
||||
// is defined (def of a sub-register is a read/mod/write of the
|
||||
// larger registers). Ignore.
|
||||
Kills.push_back(MO.getReg());
|
||||
}
|
||||
|
||||
// If any physical regs are earlyclobber, spill any value they might
|
||||
@ -830,45 +843,45 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
|
||||
// If any virtual regs are earlyclobber, allocate them now (before
|
||||
// freeing inputs that are killed).
|
||||
if (MI->isInlineAsm()) {
|
||||
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
|
||||
MachineOperand& MO = MI->getOperand(i);
|
||||
if (MO.isReg() && MO.isDef() && MO.isEarlyClobber() &&
|
||||
MO.getReg()) {
|
||||
if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
|
||||
unsigned DestVirtReg = MO.getReg();
|
||||
unsigned DestPhysReg;
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (!MO.isReg() || !MO.isDef() || !MO.isEarlyClobber() ||
|
||||
!MO.getReg())
|
||||
continue;
|
||||
|
||||
if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
|
||||
unsigned DestVirtReg = MO.getReg();
|
||||
unsigned DestPhysReg;
|
||||
|
||||
// If DestVirtReg already has a value, use it.
|
||||
if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
|
||||
DestPhysReg = getReg(MBB, MI, DestVirtReg);
|
||||
MF->getRegInfo().setPhysRegUsed(DestPhysReg);
|
||||
markVirtRegModified(DestVirtReg);
|
||||
getVirtRegLastUse(DestVirtReg) =
|
||||
std::make_pair((MachineInstr*)0, 0);
|
||||
DEBUG(dbgs() << " Assigning " << TRI->getName(DestPhysReg)
|
||||
<< " to %reg" << DestVirtReg << "\n");
|
||||
MO.setReg(DestPhysReg); // Assign the earlyclobber register
|
||||
} else {
|
||||
unsigned Reg = MO.getReg();
|
||||
if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
|
||||
// These are extra physical register defs when a sub-register
|
||||
// is defined (def of a sub-register is a read/mod/write of the
|
||||
// larger registers). Ignore.
|
||||
if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
|
||||
// If DestVirtReg already has a value, use it.
|
||||
if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
|
||||
DestPhysReg = getReg(MBB, MI, DestVirtReg);
|
||||
MF->getRegInfo().setPhysRegUsed(DestPhysReg);
|
||||
markVirtRegModified(DestVirtReg);
|
||||
getVirtRegLastUse(DestVirtReg) =
|
||||
std::make_pair((MachineInstr*)0, 0);
|
||||
DEBUG(dbgs() << " Assigning " << TRI->getName(DestPhysReg)
|
||||
<< " to %reg" << DestVirtReg << "\n");
|
||||
MO.setReg(DestPhysReg); // Assign the earlyclobber register
|
||||
} else {
|
||||
unsigned Reg = MO.getReg();
|
||||
if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
|
||||
// These are extra physical register defs when a sub-register
|
||||
// is defined (def of a sub-register is a read/mod/write of the
|
||||
// larger registers). Ignore.
|
||||
if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
|
||||
|
||||
MF->getRegInfo().setPhysRegUsed(Reg);
|
||||
spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
|
||||
PhysRegsUsed[Reg] = 0; // It is free and reserved now
|
||||
AddToPhysRegsUseOrder(Reg);
|
||||
MF->getRegInfo().setPhysRegUsed(Reg);
|
||||
spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
|
||||
PhysRegsUsed[Reg] = 0; // It is free and reserved now
|
||||
AddToPhysRegsUseOrder(Reg);
|
||||
|
||||
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
|
||||
*SubRegs; ++SubRegs) {
|
||||
if (PhysRegsUsed[*SubRegs] != -2) {
|
||||
MF->getRegInfo().setPhysRegUsed(*SubRegs);
|
||||
PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
|
||||
AddToPhysRegsUseOrder(*SubRegs);
|
||||
}
|
||||
}
|
||||
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
|
||||
*SubRegs; ++SubRegs) {
|
||||
if (PhysRegsUsed[*SubRegs] == -2) continue;
|
||||
MF->getRegInfo().setPhysRegUsed(*SubRegs);
|
||||
PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
|
||||
AddToPhysRegsUseOrder(*SubRegs);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -894,7 +907,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
|
||||
//
|
||||
SmallSet<unsigned, 4> ReloadedRegs;
|
||||
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
|
||||
MachineOperand& MO = MI->getOperand(i);
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
// here we are looking for only used operands (never def&use)
|
||||
if (MO.isReg() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
|
||||
TargetRegisterInfo::isVirtualRegister(MO.getReg()))
|
||||
@ -923,18 +936,18 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
|
||||
"Silently clearing a virtual register?");
|
||||
}
|
||||
|
||||
if (PhysReg) {
|
||||
DEBUG(dbgs() << " Last use of " << TRI->getName(PhysReg)
|
||||
<< "[%reg" << VirtReg <<"], removing it from live set\n");
|
||||
removePhysReg(PhysReg);
|
||||
for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
|
||||
*SubRegs; ++SubRegs) {
|
||||
if (PhysRegsUsed[*SubRegs] != -2) {
|
||||
DEBUG(dbgs() << " Last use of "
|
||||
<< TRI->getName(*SubRegs) << "[%reg" << VirtReg
|
||||
<<"], removing it from live set\n");
|
||||
removePhysReg(*SubRegs);
|
||||
}
|
||||
if (!PhysReg) continue;
|
||||
|
||||
DEBUG(dbgs() << " Last use of " << TRI->getName(PhysReg)
|
||||
<< "[%reg" << VirtReg <<"], removing it from live set\n");
|
||||
removePhysReg(PhysReg);
|
||||
for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
|
||||
*SubRegs; ++SubRegs) {
|
||||
if (PhysRegsUsed[*SubRegs] != -2) {
|
||||
DEBUG(dbgs() << " Last use of "
|
||||
<< TRI->getName(*SubRegs) << "[%reg" << VirtReg
|
||||
<<"], removing it from live set\n");
|
||||
removePhysReg(*SubRegs);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -942,30 +955,31 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
|
||||
// Loop over all of the operands of the instruction, spilling registers that
|
||||
// are defined, and marking explicit destinations in the PhysRegsUsed map.
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
MachineOperand& MO = MI->getOperand(i);
|
||||
if (MO.isReg() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
|
||||
!MO.isEarlyClobber() &&
|
||||
TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
|
||||
unsigned Reg = MO.getReg();
|
||||
if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
|
||||
// These are extra physical register defs when a sub-register
|
||||
// is defined (def of a sub-register is a read/mod/write of the
|
||||
// larger registers). Ignore.
|
||||
if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (!MO.isReg() || !MO.isDef() || MO.isImplicit() || !MO.getReg() ||
|
||||
MO.isEarlyClobber() ||
|
||||
!TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
|
||||
continue;
|
||||
|
||||
unsigned Reg = MO.getReg();
|
||||
if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
|
||||
// These are extra physical register defs when a sub-register
|
||||
// is defined (def of a sub-register is a read/mod/write of the
|
||||
// larger registers). Ignore.
|
||||
if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
|
||||
|
||||
MF->getRegInfo().setPhysRegUsed(Reg);
|
||||
spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
|
||||
PhysRegsUsed[Reg] = 0; // It is free and reserved now
|
||||
AddToPhysRegsUseOrder(Reg);
|
||||
MF->getRegInfo().setPhysRegUsed(Reg);
|
||||
spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
|
||||
PhysRegsUsed[Reg] = 0; // It is free and reserved now
|
||||
AddToPhysRegsUseOrder(Reg);
|
||||
|
||||
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
|
||||
*SubRegs; ++SubRegs) {
|
||||
if (PhysRegsUsed[*SubRegs] != -2) {
|
||||
MF->getRegInfo().setPhysRegUsed(*SubRegs);
|
||||
PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
|
||||
AddToPhysRegsUseOrder(*SubRegs);
|
||||
}
|
||||
}
|
||||
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
|
||||
*SubRegs; ++SubRegs) {
|
||||
if (PhysRegsUsed[*SubRegs] == -2) continue;
|
||||
|
||||
MF->getRegInfo().setPhysRegUsed(*SubRegs);
|
||||
PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
|
||||
AddToPhysRegsUseOrder(*SubRegs);
|
||||
}
|
||||
}
|
||||
|
||||
@ -982,18 +996,18 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
|
||||
MF->getRegInfo().setPhysRegUsed(Reg);
|
||||
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
|
||||
*SubRegs; ++SubRegs) {
|
||||
if (PhysRegsUsed[*SubRegs] != -2) {
|
||||
AddToPhysRegsUseOrder(*SubRegs);
|
||||
PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
|
||||
MF->getRegInfo().setPhysRegUsed(*SubRegs);
|
||||
}
|
||||
if (PhysRegsUsed[*SubRegs] == -2) continue;
|
||||
|
||||
AddToPhysRegsUseOrder(*SubRegs);
|
||||
PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
|
||||
MF->getRegInfo().setPhysRegUsed(*SubRegs);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
SmallVector<unsigned, 8> DeadDefs;
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
MachineOperand& MO = MI->getOperand(i);
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (MO.isReg() && MO.isDead())
|
||||
DeadDefs.push_back(MO.getReg());
|
||||
}
|
||||
@ -1004,45 +1018,46 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
|
||||
// we need to scavenge a register.
|
||||
//
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
MachineOperand& MO = MI->getOperand(i);
|
||||
if (MO.isReg() && MO.isDef() && MO.getReg() &&
|
||||
!MO.isEarlyClobber() &&
|
||||
TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
|
||||
unsigned DestVirtReg = MO.getReg();
|
||||
unsigned DestPhysReg;
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (!MO.isReg() || !MO.isDef() || !MO.getReg() ||
|
||||
MO.isEarlyClobber() ||
|
||||
!TargetRegisterInfo::isVirtualRegister(MO.getReg()))
|
||||
continue;
|
||||
|
||||
unsigned DestVirtReg = MO.getReg();
|
||||
unsigned DestPhysReg;
|
||||
|
||||
// If DestVirtReg already has a value, use it.
|
||||
if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg))) {
|
||||
// If this is a copy try to reuse the input as the output;
|
||||
// that will make the copy go away.
|
||||
// If this is a copy, the source reg is a phys reg, and
|
||||
// that reg is available, use that phys reg for DestPhysReg.
|
||||
// If this is a copy, the source reg is a virtual reg, and
|
||||
// the phys reg that was assigned to that virtual reg is now
|
||||
// available, use that phys reg for DestPhysReg. (If it's now
|
||||
// available that means this was the last use of the source.)
|
||||
if (isCopy &&
|
||||
TargetRegisterInfo::isPhysicalRegister(SrcCopyReg) &&
|
||||
isPhysRegAvailable(SrcCopyReg)) {
|
||||
DestPhysReg = SrcCopyReg;
|
||||
assignVirtToPhysReg(DestVirtReg, DestPhysReg);
|
||||
} else if (isCopy &&
|
||||
TargetRegisterInfo::isVirtualRegister(SrcCopyReg) &&
|
||||
SrcCopyPhysReg && isPhysRegAvailable(SrcCopyPhysReg) &&
|
||||
MF->getRegInfo().getRegClass(DestVirtReg)->
|
||||
contains(SrcCopyPhysReg)) {
|
||||
DestPhysReg = SrcCopyPhysReg;
|
||||
assignVirtToPhysReg(DestVirtReg, DestPhysReg);
|
||||
} else
|
||||
DestPhysReg = getReg(MBB, MI, DestVirtReg);
|
||||
}
|
||||
MF->getRegInfo().setPhysRegUsed(DestPhysReg);
|
||||
markVirtRegModified(DestVirtReg);
|
||||
getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0);
|
||||
DEBUG(dbgs() << " Assigning " << TRI->getName(DestPhysReg)
|
||||
<< " to %reg" << DestVirtReg << "\n");
|
||||
MO.setReg(DestPhysReg); // Assign the output register
|
||||
// If DestVirtReg already has a value, use it.
|
||||
if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg))) {
|
||||
// If this is a copy try to reuse the input as the output;
|
||||
// that will make the copy go away.
|
||||
// If this is a copy, the source reg is a phys reg, and
|
||||
// that reg is available, use that phys reg for DestPhysReg.
|
||||
// If this is a copy, the source reg is a virtual reg, and
|
||||
// the phys reg that was assigned to that virtual reg is now
|
||||
// available, use that phys reg for DestPhysReg. (If it's now
|
||||
// available that means this was the last use of the source.)
|
||||
if (isCopy &&
|
||||
TargetRegisterInfo::isPhysicalRegister(SrcCopyReg) &&
|
||||
isPhysRegAvailable(SrcCopyReg)) {
|
||||
DestPhysReg = SrcCopyReg;
|
||||
assignVirtToPhysReg(DestVirtReg, DestPhysReg);
|
||||
} else if (isCopy &&
|
||||
TargetRegisterInfo::isVirtualRegister(SrcCopyReg) &&
|
||||
SrcCopyPhysReg && isPhysRegAvailable(SrcCopyPhysReg) &&
|
||||
MF->getRegInfo().getRegClass(DestVirtReg)->
|
||||
contains(SrcCopyPhysReg)) {
|
||||
DestPhysReg = SrcCopyPhysReg;
|
||||
assignVirtToPhysReg(DestVirtReg, DestPhysReg);
|
||||
} else
|
||||
DestPhysReg = getReg(MBB, MI, DestVirtReg);
|
||||
}
|
||||
MF->getRegInfo().setPhysRegUsed(DestPhysReg);
|
||||
markVirtRegModified(DestVirtReg);
|
||||
getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0);
|
||||
DEBUG(dbgs() << " Assigning " << TRI->getName(DestPhysReg)
|
||||
<< " to %reg" << DestVirtReg << "\n");
|
||||
MO.setReg(DestPhysReg); // Assign the output register
|
||||
}
|
||||
|
||||
// If this instruction defines any registers that are immediately dead,
|
||||
@ -1059,21 +1074,20 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
|
||||
} else if (PhysRegsUsed[PhysReg] == -2) {
|
||||
// Unallocatable register dead, ignore.
|
||||
continue;
|
||||
}
|
||||
|
||||
if (PhysReg) {
|
||||
DEBUG(dbgs() << " Register " << TRI->getName(PhysReg)
|
||||
<< " [%reg" << VirtReg
|
||||
<< "] is never used, removing it from live set\n");
|
||||
removePhysReg(PhysReg);
|
||||
for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
|
||||
*AliasSet; ++AliasSet) {
|
||||
if (PhysRegsUsed[*AliasSet] != -2) {
|
||||
DEBUG(dbgs() << " Register " << TRI->getName(*AliasSet)
|
||||
<< " [%reg" << *AliasSet
|
||||
<< "] is never used, removing it from live set\n");
|
||||
removePhysReg(*AliasSet);
|
||||
}
|
||||
} else if (!PhysReg)
|
||||
continue;
|
||||
|
||||
DEBUG(dbgs() << " Register " << TRI->getName(PhysReg)
|
||||
<< " [%reg" << VirtReg
|
||||
<< "] is never used, removing it from live set\n");
|
||||
removePhysReg(PhysReg);
|
||||
for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
|
||||
*AliasSet; ++AliasSet) {
|
||||
if (PhysRegsUsed[*AliasSet] != -2) {
|
||||
DEBUG(dbgs() << " Register " << TRI->getName(*AliasSet)
|
||||
<< " [%reg" << *AliasSet
|
||||
<< "] is never used, removing it from live set\n");
|
||||
removePhysReg(*AliasSet);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1143,8 +1157,10 @@ bool RALocal::runOnMachineFunction(MachineFunction &Fn) {
|
||||
StackSlotForVirtReg.grow(LastVirtReg);
|
||||
Virt2PhysRegMap.grow(LastVirtReg);
|
||||
Virt2LastUseMap.grow(LastVirtReg);
|
||||
VirtRegModified.resize(LastVirtReg+1-TargetRegisterInfo::FirstVirtualRegister);
|
||||
UsedInMultipleBlocks.resize(LastVirtReg+1-TargetRegisterInfo::FirstVirtualRegister);
|
||||
VirtRegModified.resize(LastVirtReg+1 -
|
||||
TargetRegisterInfo::FirstVirtualRegister);
|
||||
UsedInMultipleBlocks.resize(LastVirtReg+1 -
|
||||
TargetRegisterInfo::FirstVirtualRegister);
|
||||
|
||||
// Loop over all of the basic blocks, eliminating virtual register references
|
||||
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
|
||||
|
||||
Loading…
Reference in New Issue
Block a user