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Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} instructions.
This adds a new decoder table/namespace 'VFPV8', as these instructions have their top 4 bits as 0b1111, while other Thumb instructions have 0b1110. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185642 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Joey Gouly
parent
3c99602ca8
commit
4ea250524f
@ -1548,6 +1548,35 @@ class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
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let Inst{4} = op4;
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}
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// FP, binary, not predicated
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class ADbInp<bits<5> opcod1, bits<2> opcod2, dag oops, dag iops,
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InstrItinClass itin, string asm, list<dag> pattern>
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: VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone,
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VFPBinaryFrm, itin, asm, "", pattern>
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{
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// Instruction operands.
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bits<5> Dd;
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bits<5> Dn;
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bits<5> Dm;
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let Inst{31-28} = 0b1111;
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// Encode instruction operands.
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let Inst{3-0} = Dm{3-0};
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let Inst{5} = Dm{4};
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let Inst{19-16} = Dn{3-0};
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let Inst{7} = Dn{4};
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let Inst{15-12} = Dd{3-0};
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let Inst{22} = Dd{4};
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let Inst{27-23} = opcod1;
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let Inst{21-20} = opcod2;
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let Inst{11-9} = 0b101;
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let Inst{8} = 1; // double precision
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let Inst{6} = 0;
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let Inst{4} = 0;
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}
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// Single precision, unary
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class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
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bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
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@ -1607,6 +1636,35 @@ class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
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let Inst{4} = op4;
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}
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// Single precision, binary, not predicated
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class ASbInp<bits<5> opcod1, bits<2> opcod2, dag oops, dag iops,
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InstrItinClass itin, string asm, list<dag> pattern>
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: VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone,
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VFPBinaryFrm, itin, asm, "", pattern>
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{
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// Instruction operands.
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bits<5> Sd;
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bits<5> Sn;
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bits<5> Sm;
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let Inst{31-28} = 0b1111;
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// Encode instruction operands.
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let Inst{3-0} = Sm{4-1};
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let Inst{5} = Sm{0};
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let Inst{19-16} = Sn{4-1};
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let Inst{7} = Sn{0};
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let Inst{15-12} = Sd{4-1};
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let Inst{22} = Sd{0};
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let Inst{27-23} = opcod1;
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let Inst{21-20} = opcod2;
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let Inst{11-9} = 0b101;
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let Inst{8} = 0; // Single precision
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let Inst{6} = 0;
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let Inst{4} = 0;
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}
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// Single precision binary, if no NEON. Same as ASbI except not available if
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// NEON is enabled.
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class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
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@ -333,6 +333,25 @@ def VNMULS : ASbI<0b11100, 0b10, 1, 0,
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let D = VFPNeonA8Domain;
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}
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multiclass vsel_inst<string op, bits<2> opc> {
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let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in {
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def S : ASbInp<0b11100, opc,
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(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
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NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
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[]>, Requires<[HasV8FP]>;
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def D : ADbInp<0b11100, opc,
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(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
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NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"),
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[]>, Requires<[HasV8FP]>;
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}
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}
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defm VSELGT : vsel_inst<"gt", 0b11>;
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defm VSELGE : vsel_inst<"ge", 0b10>;
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defm VSELEQ : vsel_inst<"eq", 0b00>;
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defm VSELVS : vsel_inst<"vs", 0b01>;
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// Match reassociated forms only if not sign dependent rounding.
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def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
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(VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
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@ -4905,7 +4905,7 @@ StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
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Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
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Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
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Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
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Mnemonic == "fmuls")
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Mnemonic == "fmuls" || Mnemonic.startswith("vsel"))
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return Mnemonic;
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// First, split out any predication code. Ignore mnemonics we know aren't
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@ -5005,7 +5005,7 @@ getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
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if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
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Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
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Mnemonic == "trap" || Mnemonic == "setend" ||
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Mnemonic.startswith("cps")) {
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Mnemonic.startswith("cps") || Mnemonic.startswith("vsel")) {
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// These mnemonics are never predicable
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CanAcceptPredicationCode = false;
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} else if (!isThumb()) {
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@ -455,6 +455,13 @@ DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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return result;
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}
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MI.clear();
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result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI);
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if (result != MCDisassembler::Fail) {
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Size = 4;
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return result;
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}
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MI.clear();
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result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
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this, STI);
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@ -764,6 +771,14 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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}
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}
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MI.clear();
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result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI);
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if (result != MCDisassembler::Fail) {
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Size = 4;
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UpdateThumbVFPPredicate(MI);
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return result;
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}
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if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
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MI.clear();
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result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
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@ -21,3 +21,21 @@
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@ CHECK: vcvtbeq.f64.f16 d3, s1 @ encoding: [0x60,0x3b,0xb2,0x0e]
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vcvtblt.f16.f64 s4, d1
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@ CHECK: vcvtblt.f16.f64 s4, d1 @ encoding: [0x41,0x2b,0xb3,0xbe]
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@ VSEL
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vselge.f32 s4, s1, s23
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@ CHECK: vselge.f32 s4, s1, s23 @ encoding: [0xab,0x2a,0x20,0xfe]
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vselge.f64 d30, d31, d23
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@ CHECK: vselge.f64 d30, d31, d23 @ encoding: [0xa7,0xeb,0x6f,0xfe]
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vselgt.f32 s0, s1, s0
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@ CHECK: vselgt.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xfe]
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vselgt.f64 d5, d10, d20
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@ CHECK: vselgt.f64 d5, d10, d20 @ encoding: [0x24,0x5b,0x3a,0xfe]
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vseleq.f32 s30, s28, s23
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@ CHECK: vseleq.f32 s30, s28, s23 @ encoding: [0x2b,0xfa,0x0e,0xfe]
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vseleq.f64 d2, d4, d8
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@ CHECK: vseleq.f64 d2, d4, d8 @ encoding: [0x08,0x2b,0x04,0xfe]
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vselvs.f32 s21, s16, s14
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@ CHECK: vselvs.f32 s21, s16, s14 @ encoding: [0x07,0xaa,0x58,0xfe]
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vselvs.f64 d0, d1, d31
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@ CHECK: vselvs.f64 d0, d1, d31 @ encoding: [0x2f,0x0b,0x11,0xfe]
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@ -23,3 +23,28 @@
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0x41 0x2b 0xb3 0xbe
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# CHECK: vcvtblt.f16.f64 s4, d1
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0xab 0x2a 0x20 0xfe
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# CHECK: vselge.f32 s4, s1, s23
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0xa7 0xeb 0x6f 0xfe
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# CHECK: vselge.f64 d30, d31, d23
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0x80 0x0a 0x30 0xfe
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# CHECK: vselgt.f32 s0, s1, s0
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0x24 0x5b 0x3a 0xfe
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# CHECK: vselgt.f64 d5, d10, d20
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0x2b 0xfa 0x0e 0xfe
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# CHECK: vseleq.f32 s30, s28, s23
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0x08 0x2b 0x04 0xfe
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# CHECK: vseleq.f64 d2, d4, d8
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0x07 0xaa 0x58 0xfe
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# CHECK: vselvs.f32 s21, s16, s14
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0x2f 0x0b 0x11 0xfe
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# CHECK: vselvs.f64 d0, d1, d31
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