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[AMDGPU] Assembler: Fix VOP3 only instructions
Separate methods to convert parsed instructions to MCInst:
- VOP3 only instructions (always create modifiers as operands in MCInst)
- VOP2 instrunctions with modifiers (create modifiers as operands
in MCInst when e64 encoding is forced or modifiers are parsed)
- VOP2 instructions without modifiers (do not create modifiers
as operands in MCInst)
- Add VOP3Only flag. Pass HasMods flag to VOP3Common.
- Simplify code that deals with modifiers (-1 is now same as
0). This is no longer needed.
- Add few tests (more will be added separately).
Update error message now correct.
Patch By: Nikolay Haustov
Differential Revision: http://reviews.llvm.org/D16778
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260483 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
parent
e48f9ae77d
commit
4ea8ee7c76
@ -116,8 +116,7 @@ public:
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}
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void addRegWithInputModsOperands(MCInst &Inst, unsigned N) const {
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Inst.addOperand(MCOperand::createImm(
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Reg.Modifiers == -1 ? 0 : Reg.Modifiers));
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Inst.addOperand(MCOperand::createImm(Reg.Modifiers));
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addRegOperands(Inst, N);
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}
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@ -176,11 +175,23 @@ public:
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}
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bool isReg() const override {
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return Kind == Register && Reg.Modifiers == -1;
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return Kind == Register && Reg.Modifiers == 0;
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}
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bool isRegWithInputMods() const {
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return Kind == Register && (Reg.IsForcedVOP3 || Reg.Modifiers != -1);
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return Kind == Register;
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}
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bool isClamp() const {
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return isImm() && Imm.Type == ImmTyClamp;
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}
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bool isOMod() const {
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return isImm() && Imm.Type == ImmTyOMod;
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}
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bool isMod() const {
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return isClamp() || isOMod();
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}
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void setModifiers(unsigned Mods) {
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@ -190,7 +201,7 @@ public:
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bool hasModifiers() const {
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assert(isRegKind());
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return Reg.Modifiers != -1;
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return Reg.Modifiers != 0;
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}
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unsigned getReg() const override {
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@ -202,7 +213,7 @@ public:
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}
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bool isRegClass(unsigned RCID) const {
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return Reg.TRI->getRegClass(RCID).contains(getReg());
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return isReg() && Reg.TRI->getRegClass(RCID).contains(getReg());
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}
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bool isSCSrc32() const {
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@ -306,7 +317,7 @@ public:
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Op->Reg.RegNo = RegNo;
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Op->Reg.TRI = TRI;
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Op->Reg.STI = STI;
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Op->Reg.Modifiers = -1;
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Op->Reg.Modifiers = 0;
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Op->Reg.IsForcedVOP3 = ForceVOP3;
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Op->StartLoc = S;
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Op->EndLoc = E;
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@ -462,6 +473,10 @@ public:
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OperandMatchResultTy parseUNorm(OperandVector &Operands);
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OperandMatchResultTy parseR128(OperandVector &Operands);
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void cvtId(MCInst &Inst, const OperandVector &Operands);
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void cvtVOP3_2_mod(MCInst &Inst, const OperandVector &Operands);
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void cvtVOP3_2_nomod(MCInst &Inst, const OperandVector &Operands);
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void cvtVOP3_only(MCInst &Inst, const OperandVector &Operands);
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void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
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OperandMatchResultTy parseVOP3OptionalOps(OperandVector &Operands);
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};
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@ -1103,7 +1118,7 @@ AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
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// If we are parsing after we reach EndOfStatement then this means we
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// are appending default values to the Operands list. This is only done
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// by custom parser, so we shouldn't continue on to the generic parsing.
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if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail ||
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if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail||
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getLexer().is(AsmToken::EndOfStatement))
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return ResTy;
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@ -1153,8 +1168,6 @@ AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
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SMLoc S, E;
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unsigned RegNo;
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if (!ParseRegister(RegNo, S, E)) {
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bool HasModifiers = operandsHaveModifiers(Operands);
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unsigned Modifiers = 0;
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if (Negate)
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@ -1167,34 +1180,23 @@ AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
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Modifiers |= 0x2;
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}
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if (Modifiers && !HasModifiers) {
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// We are adding a modifier to src1 or src2 and previous sources
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// don't have modifiers, so we need to go back and empty modifers
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// for each previous source.
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for (unsigned PrevRegIdx = Operands.size() - 1; PrevRegIdx > 1;
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--PrevRegIdx) {
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AMDGPUOperand &RegOp = ((AMDGPUOperand&)*Operands[PrevRegIdx]);
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RegOp.setModifiers(0);
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}
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}
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Operands.push_back(AMDGPUOperand::CreateReg(
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RegNo, S, E, getContext().getRegisterInfo(), &getSTI(),
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isForcedVOP3()));
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if (HasModifiers || Modifiers) {
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if (Modifiers) {
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AMDGPUOperand &RegOp = ((AMDGPUOperand&)*Operands[Operands.size() - 1]);
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RegOp.setModifiers(Modifiers);
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}
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} else {
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Operands.push_back(AMDGPUOperand::CreateToken(Parser.getTok().getString(),
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S));
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Parser.Lex();
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}
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return MatchOperand_Success;
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} else {
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ResTy = parseVOP3OptionalOps(Operands);
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if (ResTy == MatchOperand_NoMatch) {
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Operands.push_back(AMDGPUOperand::CreateToken(Parser.getTok().getString(),
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S));
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Parser.Lex();
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}
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}
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return MatchOperand_Success;
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}
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default:
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return MatchOperand_NoMatch;
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@ -1802,10 +1804,12 @@ static bool isVOP3(OperandVector &Operands) {
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if (operandsHaveModifiers(Operands))
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return true;
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AMDGPUOperand &DstOp = ((AMDGPUOperand&)*Operands[1]);
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if (Operands.size() >= 2) {
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AMDGPUOperand &DstOp = ((AMDGPUOperand&)*Operands[1]);
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if (DstOp.isReg() && DstOp.isRegClass(AMDGPU::SGPR_64RegClassID))
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return true;
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if (DstOp.isReg() && DstOp.isRegClass(AMDGPU::SGPR_64RegClassID))
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return true;
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}
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if (Operands.size() >= 5)
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return true;
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@ -1848,35 +1852,70 @@ AMDGPUAsmParser::parseVOP3OptionalOps(OperandVector &Operands) {
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return MatchOperand_NoMatch;
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}
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void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
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unsigned i = 1;
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void AMDGPUAsmParser::cvtId(MCInst &Inst, const OperandVector &Operands) {
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unsigned I = 1;
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const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
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if (Desc.getNumDefs() > 0) {
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((AMDGPUOperand &)*Operands[i++]).addRegOperands(Inst, 1);
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((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
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}
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for (unsigned E = Operands.size(); I != E; ++I)
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((AMDGPUOperand &)*Operands[I]).addRegOrImmOperands(Inst, 1);
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}
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void AMDGPUAsmParser::cvtVOP3_2_mod(MCInst &Inst, const OperandVector &Operands) {
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if (operandsHaveModifiers(Operands) || isForcedVOP3()) {
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cvtVOP3(Inst, Operands);
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} else {
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cvtId(Inst, Operands);
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}
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}
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void AMDGPUAsmParser::cvtVOP3_2_nomod(MCInst &Inst, const OperandVector &Operands) {
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if (operandsHaveModifiers(Operands)) {
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cvtVOP3(Inst, Operands);
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} else {
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cvtId(Inst, Operands);
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}
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}
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void AMDGPUAsmParser::cvtVOP3_only(MCInst &Inst, const OperandVector &Operands) {
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cvtVOP3(Inst, Operands);
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}
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void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
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unsigned I = 1;
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const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
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if (Desc.getNumDefs() > 0) {
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((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
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}
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std::map<enum AMDGPUOperand::ImmTy, unsigned> OptionalIdx;
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if (operandsHaveModifiers(Operands)) {
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for (unsigned e = Operands.size(); i != e; ++i) {
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AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
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if (Op.isRegWithInputMods()) {
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((AMDGPUOperand &)*Operands[i]).addRegWithInputModsOperands(Inst, 2);
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continue;
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}
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OptionalIdx[Op.getImmTy()] = i;
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unsigned ClampIdx = 0, OModIdx = 0;
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for (unsigned E = Operands.size(); I != E; ++I) {
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AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
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if (Op.isRegWithInputMods()) {
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Op.addRegWithInputModsOperands(Inst, 2);
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} else if (Op.isClamp()) {
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ClampIdx = I;
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} else if (Op.isOMod()) {
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OModIdx = I;
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} else if (Op.isImm()) {
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Op.addImmOperands(Inst, 1);
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} else {
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assert(false);
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}
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}
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unsigned ClampIdx = OptionalIdx[AMDGPUOperand::ImmTyClamp];
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unsigned OModIdx = OptionalIdx[AMDGPUOperand::ImmTyOMod];
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((AMDGPUOperand &)*Operands[ClampIdx]).addImmOperands(Inst, 1);
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((AMDGPUOperand &)*Operands[OModIdx]).addImmOperands(Inst, 1);
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if (ClampIdx) {
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AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[ClampIdx]);
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Op.addImmOperands(Inst, 1);
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} else {
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for (unsigned e = Operands.size(); i != e; ++i)
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((AMDGPUOperand &)*Operands[i]).addRegOrImmOperands(Inst, 1);
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Inst.addOperand(MCOperand::createImm(0));
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}
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if (OModIdx) {
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AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[OModIdx]);
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Op.addImmOperands(Inst, 1);
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} else {
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Inst.addOperand(MCOperand::createImm(0));
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}
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}
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@ -123,7 +123,7 @@ class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> :
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let Size = 4;
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}
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class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
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class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern, bit HasMods = 0, bit VOP3Only = 0> :
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VOPAnyCommon <outs, ins, asm, pattern> {
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// Using complex patterns gives VOP3 patterns a very high complexity rating,
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@ -135,7 +135,10 @@ class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
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let VOP3 = 1;
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let VALU = 1;
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let AsmMatchConverter = "cvtVOP3";
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let AsmMatchConverter =
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!if(!eq(VOP3Only,1),
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"cvtVOP3_only",
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!if(!eq(HasMods,1), "cvtVOP3_2_mod", "cvtVOP3_2_nomod"));
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let isCodeGenOnly = 0;
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int Size = 8;
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@ -477,6 +477,7 @@ def OModMatchClass : AsmOperandClass {
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let PredicateMethod = "isImm";
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let ParserMethod = "parseVOP3OptionalOps";
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let RenderMethod = "addImmOperands";
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let IsOptional = 1;
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}
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def ClampMatchClass : AsmOperandClass {
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@ -484,6 +485,7 @@ def ClampMatchClass : AsmOperandClass {
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let PredicateMethod = "isImm";
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let ParserMethod = "parseVOP3OptionalOps";
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let RenderMethod = "addImmOperands";
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let IsOptional = 1;
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}
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class SMRDOffsetBaseMatchClass <string predicate> : AsmOperandClass {
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@ -1072,8 +1074,10 @@ class getVOP3SrcForVT<ValueType VT> {
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// Returns 1 if the source arguments have modifiers, 0 if they do not.
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// XXX - do f16 instructions?
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class hasModifiers<ValueType SrcVT> {
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bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
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!if(!eq(SrcVT.Value, f64.Value), 1, 0));
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bit ret =
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!if(!eq(SrcVT.Value, f32.Value), 1,
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!if(!eq(SrcVT.Value, f64.Value), 1,
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0));
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}
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// Returns the input arguments for VOP[12C] instructions for the given SrcVT.
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@ -1471,8 +1475,9 @@ class VOP3DisableModFields <bit HasSrc0Mods,
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bits<1> clamp = !if(HasOutputMods, ?, 0);
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}
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class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
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VOP3Common <outs, ins, "", pattern>,
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class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName,
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bit HasMods = 0, bit VOP3Only = 0> :
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VOP3Common <outs, ins, "", pattern, HasMods, VOP3Only>,
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VOP <opName>,
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SIMCInstr<opName#"_e64", SISubtarget.NONE>,
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MnemonicAlias<opName#"_e64", opName> {
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@ -1483,44 +1488,48 @@ class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
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field bit src0;
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}
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class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
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VOP3Common <outs, ins, asm, []>,
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class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName,
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bit HasMods = 0, bit VOP3Only = 0> :
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VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>,
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VOP3e <op>,
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SIMCInstr<opName#"_e64", SISubtarget.SI> {
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let AssemblerPredicates = [isSICI];
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}
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class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
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VOP3Common <outs, ins, asm, []>,
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class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName,
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bit HasMods = 0, bit VOP3Only = 0> :
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VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>,
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VOP3e_vi <op>,
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SIMCInstr <opName#"_e64", SISubtarget.VI> {
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let AssemblerPredicates = [isVI];
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}
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class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
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VOP3Common <outs, ins, asm, []>,
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class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName,
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bit HasMods = 0, bit VOP3Only = 0> :
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VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>,
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VOP3be <op>,
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SIMCInstr<opName#"_e64", SISubtarget.SI> {
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let AssemblerPredicates = [isSICI];
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}
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class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
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VOP3Common <outs, ins, asm, []>,
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class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName,
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bit HasMods = 0, bit VOP3Only = 0> :
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VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>,
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VOP3be_vi <op>,
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SIMCInstr <opName#"_e64", SISubtarget.VI> {
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let AssemblerPredicates = [isVI];
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}
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multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
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string opName, int NumSrcArgs, bit HasMods = 1> {
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string opName, int NumSrcArgs, bit HasMods = 1, bit VOP3Only = 0> {
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def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
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def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
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def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName, HasMods, VOP3Only>,
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VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
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!if(!eq(NumSrcArgs, 2), 0, 1),
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HasMods>;
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def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
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def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName, HasMods, VOP3Only>,
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VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
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!if(!eq(NumSrcArgs, 2), 0, 1),
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HasMods>;
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@ -1529,21 +1538,21 @@ multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
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multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
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list<dag> pattern, string opName, bit HasMods = 1> {
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def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
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def "" : VOP3_Pseudo <outs, ins, pattern, opName, HasMods>;
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def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
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def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName, HasMods>,
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VOP3DisableFields<0, 0, HasMods>;
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def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
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def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName, HasMods>,
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VOP3DisableFields<0, 0, HasMods>;
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}
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multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
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list<dag> pattern, string opName, bit HasMods = 1> {
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||||
def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
|
||||
def "" : VOP3_Pseudo <outs, ins, pattern, opName, HasMods>;
|
||||
|
||||
def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
|
||||
def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName, HasMods>,
|
||||
VOP3DisableFields<0, 0, HasMods>;
|
||||
// No VI instruction. This class is for SI only.
|
||||
}
|
||||
@ -1552,13 +1561,13 @@ multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, string opName, string revOp,
|
||||
bit HasMods = 1> {
|
||||
|
||||
def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
|
||||
def "" : VOP3_Pseudo <outs, ins, pattern, opName, HasMods>,
|
||||
VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
|
||||
|
||||
def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
|
||||
def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName, HasMods>,
|
||||
VOP3DisableFields<1, 0, HasMods>;
|
||||
|
||||
def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
|
||||
def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName, HasMods>,
|
||||
VOP3DisableFields<1, 0, HasMods>;
|
||||
}
|
||||
|
||||
@ -1566,10 +1575,10 @@ multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, string opName, string revOp,
|
||||
bit HasMods = 1> {
|
||||
|
||||
def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
|
||||
def "" : VOP3_Pseudo <outs, ins, pattern, opName, HasMods>,
|
||||
VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
|
||||
|
||||
def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
|
||||
def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName, HasMods>,
|
||||
VOP3DisableFields<1, 0, HasMods>;
|
||||
|
||||
// No VI instruction. This class is for SI only.
|
||||
@ -1594,19 +1603,19 @@ multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
|
||||
bit HasMods, bit defExec,
|
||||
string revOp, list<SchedReadWrite> sched> {
|
||||
|
||||
def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
|
||||
def "" : VOP3_Pseudo <outs, ins, pattern, opName, HasMods>,
|
||||
VOP2_REV<revOp#"_e64", !eq(revOp, opName)> {
|
||||
let Defs = !if(defExec, [EXEC], []);
|
||||
let SchedRW = sched;
|
||||
}
|
||||
|
||||
def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
|
||||
def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName, HasMods>,
|
||||
VOP3DisableFields<1, 0, HasMods> {
|
||||
let Defs = !if(defExec, [EXEC], []);
|
||||
let SchedRW = sched;
|
||||
}
|
||||
|
||||
def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
|
||||
def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName, HasMods>,
|
||||
VOP3DisableFields<1, 0, HasMods> {
|
||||
let Defs = !if(defExec, [EXEC], []);
|
||||
let SchedRW = sched;
|
||||
@ -1900,8 +1909,9 @@ multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> :
|
||||
VOPCX <op, opName, VOPC_I1_I64_I64, COND_NULL, [Write64Bit], revOp>;
|
||||
|
||||
multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
|
||||
list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
|
||||
op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods
|
||||
list<dag> pat, int NumSrcArgs, bit HasMods,
|
||||
bit VOP3Only = 0> : VOP3_m <
|
||||
op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods, VOP3Only
|
||||
>;
|
||||
|
||||
multiclass VOPC_CLASS_F32 <vopc op, string opName> :
|
||||
@ -1917,7 +1927,8 @@ multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
|
||||
VOPCClassInst <op, opName, VOPC_I1_F64_I32, 1, [WriteDoubleAdd]>;
|
||||
|
||||
multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
|
||||
SDPatternOperator node = null_frag> : VOP3_Helper <
|
||||
SDPatternOperator node = null_frag, bit VOP3Only = 0> :
|
||||
VOP3_Helper <
|
||||
op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
|
||||
!if(!eq(P.NumSrcArgs, 3),
|
||||
!if(P.HasModifiers,
|
||||
@ -1941,7 +1952,7 @@ multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
|
||||
(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
|
||||
i1:$clamp, i32:$omod))))],
|
||||
[(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
|
||||
P.NumSrcArgs, P.HasModifiers
|
||||
P.NumSrcArgs, P.HasModifiers, VOP3Only
|
||||
>;
|
||||
|
||||
// Special case for v_div_fmas_{f32|f64}, since it seems to be the
|
||||
|
||||
@ -1727,23 +1727,23 @@ let SchedRW = [WriteDoubleAdd] in {
|
||||
let isCommutable = 1 in {
|
||||
|
||||
defm V_ADD_F64 : VOP3Inst <vop3<0x164, 0x280>, "v_add_f64",
|
||||
VOP_F64_F64_F64, fadd
|
||||
VOP_F64_F64_F64, fadd, 1
|
||||
>;
|
||||
defm V_MUL_F64 : VOP3Inst <vop3<0x165, 0x281>, "v_mul_f64",
|
||||
VOP_F64_F64_F64, fmul
|
||||
VOP_F64_F64_F64, fmul, 1
|
||||
>;
|
||||
|
||||
defm V_MIN_F64 : VOP3Inst <vop3<0x166, 0x282>, "v_min_f64",
|
||||
VOP_F64_F64_F64, fminnum
|
||||
VOP_F64_F64_F64, fminnum, 1
|
||||
>;
|
||||
defm V_MAX_F64 : VOP3Inst <vop3<0x167, 0x283>, "v_max_f64",
|
||||
VOP_F64_F64_F64, fmaxnum
|
||||
VOP_F64_F64_F64, fmaxnum, 1
|
||||
>;
|
||||
|
||||
} // End isCommutable = 1
|
||||
|
||||
defm V_LDEXP_F64 : VOP3Inst <vop3<0x168, 0x284>, "v_ldexp_f64",
|
||||
VOP_F64_F64_I32, AMDGPUldexp
|
||||
VOP_F64_F64_I32, AMDGPUldexp, 1
|
||||
>;
|
||||
|
||||
} // End let SchedRW = [WriteDoubleAdd]
|
||||
|
||||
@ -198,8 +198,7 @@ v_subrev_f32 v1, v3, s5
|
||||
|
||||
v_mac_legacy_f32 v1, v3, s5
|
||||
// SICI: v_mac_legacy_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x0c,0xd2,0x03,0x0b,0x00,0x00]
|
||||
// FIXME: The error message should be: error: instruction not supported on this GPU
|
||||
// NOVI: error: invalid operand for instruction
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
|
||||
v_mul_legacy_f32 v1, v3, s5
|
||||
// SICI: v_mul_legacy_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x0e,0xd2,0x03,0x0b,0x00,0x00]
|
||||
@ -223,7 +222,51 @@ v_mad_legacy_f32 v2, v4, v6, v8
|
||||
// SICI: v_mad_legacy_f32 v2, v4, v6, v8 ; encoding: [0x02,0x00,0x80,0xd2,0x04,0x0d,0x22,0x04]
|
||||
// VI: v_mad_legacy_f32 v2, v4, v6, v8 ; encoding: [0x02,0x00,0xc0,0xd1,0x04,0x0d,0x22,0x04]
|
||||
|
||||
v_add_f64 v[0:1], v[2:3], v[5:6]
|
||||
// SICI: v_add_f64 v[0:1], v[2:3], v[5:6] ; encoding: [0x00,0x00,0xc8,0xd2,0x02,0x0b,0x02,0x00]
|
||||
// VI: v_add_f64 v[0:1], v[2:3], v[5:6] ; encoding: [0x00,0x00,0x80,0xd2,0x02,0x0b,0x02,0x00]
|
||||
|
||||
v_add_f64_e64 v[0:1], v[2:3], v[5:6]
|
||||
// SICI: v_add_f64 v[0:1], v[2:3], v[5:6] ; encoding: [0x00,0x00,0xc8,0xd2,0x02,0x0b,0x02,0x00]
|
||||
// VI: v_add_f64 v[0:1], v[2:3], v[5:6] ; encoding: [0x00,0x00,0x80,0xd2,0x02,0x0b,0x02,0x00]
|
||||
|
||||
v_add_f64 v[0:1], -v[2:3], v[5:6]
|
||||
// SICI: v_add_f64 v[0:1], -v[2:3], v[5:6] ; encoding: [0x00,0x00,0xc8,0xd2,0x02,0x0b,0x02,0x20]
|
||||
// VI: v_add_f64 v[0:1], -v[2:3], v[5:6] ; encoding: [0x00,0x00,0x80,0xd2,0x02,0x0b,0x02,0x20]
|
||||
|
||||
v_add_f64_e64 v[0:1], -v[2:3], v[5:6]
|
||||
// SICI: v_add_f64 v[0:1], -v[2:3], v[5:6] ; encoding: [0x00,0x00,0xc8,0xd2,0x02,0x0b,0x02,0x20]
|
||||
// VI: v_add_f64 v[0:1], -v[2:3], v[5:6] ; encoding: [0x00,0x00,0x80,0xd2,0x02,0x0b,0x02,0x20]
|
||||
|
||||
v_add_f64 v[0:1], v[2:3], -v[5:6]
|
||||
// SICI: v_add_f64 v[0:1], v[2:3], -v[5:6] ; encoding: [0x00,0x00,0xc8,0xd2,0x02,0x0b,0x02,0x40]
|
||||
// VI: v_add_f64 v[0:1], v[2:3], -v[5:6] ; encoding: [0x00,0x00,0x80,0xd2,0x02,0x0b,0x02,0x40]
|
||||
|
||||
v_add_f64_e64 v[0:1], v[2:3], -v[5:6]
|
||||
// SICI: v_add_f64 v[0:1], v[2:3], -v[5:6] ; encoding: [0x00,0x00,0xc8,0xd2,0x02,0x0b,0x02,0x40]
|
||||
// VI: v_add_f64 v[0:1], v[2:3], -v[5:6] ; encoding: [0x00,0x00,0x80,0xd2,0x02,0x0b,0x02,0x40]
|
||||
|
||||
v_add_f64 v[0:1], |v[2:3]|, v[5:6]
|
||||
// SICI: v_add_f64 v[0:1], |v[2:3]|, v[5:6] ; encoding: [0x00,0x01,0xc8,0xd2,0x02,0x0b,0x02,0x00]
|
||||
// VI: v_add_f64 v[0:1], |v[2:3]|, v[5:6] ; encoding: [0x00,0x01,0x80,0xd2,0x02,0x0b,0x02,0x00]
|
||||
|
||||
v_add_f64_e64 v[0:1], |v[2:3]|, v[5:6]
|
||||
// SICI: v_add_f64 v[0:1], |v[2:3]|, v[5:6] ; encoding: [0x00,0x01,0xc8,0xd2,0x02,0x0b,0x02,0x00]
|
||||
// VI: v_add_f64 v[0:1], |v[2:3]|, v[5:6] ; encoding: [0x00,0x01,0x80,0xd2,0x02,0x0b,0x02,0x00]
|
||||
|
||||
v_add_f64 v[0:1], v[2:3], |v[5:6]|
|
||||
// SICI: v_add_f64 v[0:1], v[2:3], |v[5:6]| ; encoding: [0x00,0x02,0xc8,0xd2,0x02,0x0b,0x02,0x00]
|
||||
// VI: v_add_f64 v[0:1], v[2:3], |v[5:6]| ; encoding: [0x00,0x02,0x80,0xd2,0x02,0x0b,0x02,0x00]
|
||||
|
||||
v_add_f64_e64 v[0:1], v[2:3], |v[5:6]|
|
||||
// SICI: v_add_f64 v[0:1], v[2:3], |v[5:6]| ; encoding: [0x00,0x02,0xc8,0xd2,0x02,0x0b,0x02,0x00]
|
||||
// VI: v_add_f64 v[0:1], v[2:3], |v[5:6]| ; encoding: [0x00,0x02,0x80,0xd2,0x02,0x0b,0x02,0x00]
|
||||
|
||||
v_add_f64 v[0:1], -v[2:3], |v[5:6]| clamp mul:4
|
||||
// SICI: v_add_f64 v[0:1], -v[2:3], |v[5:6]| clamp mul:4 ; encoding: [0x00,0x0a,0xc8,0xd2,0x02,0x0b,0x02,0x30]
|
||||
// VI: v_add_f64 v[0:1], -v[2:3], |v[5:6]| clamp mul:4 ; encoding: [0x00,0x82,0x80,0xd2,0x02,0x0b,0x02,0x30]
|
||||
|
||||
v_add_f64_e64 v[0:1], -v[2:3], |v[5:6]| clamp mul:4
|
||||
// SICI: v_add_f64 v[0:1], -v[2:3], |v[5:6]| clamp mul:4 ; encoding: [0x00,0x0a,0xc8,0xd2,0x02,0x0b,0x02,0x30]
|
||||
// VI: v_add_f64 v[0:1], -v[2:3], |v[5:6]| clamp mul:4 ; encoding: [0x00,0x82,0x80,0xd2,0x02,0x0b,0x02,0x30]
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user