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Thumb assembly parsing and encoding for MOV.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138076 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-08-19 20:46:54 +00:00
parent c68e927488
commit 4ec6e888ec
5 changed files with 34 additions and 5 deletions
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2
lib/Target/ARM/ARMInstrFormats.td
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@ -148,7 +148,7 @@ def iflags_op : Operand<i32> {
// ARM Predicate operand. Default to 14 = always (AL). Second part is CC
// register whose default is 0 (no register).
def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
(ops (i32 14), (i32 zero_reg))> {
let PrintMethod = "printPredicateOperand";
let ParserMatchClass = CondCodeOperand;

5
lib/Target/ARM/ARMInstrThumb.td
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@ -1014,6 +1014,11 @@ def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
let Inst{10-8} = Rd;
let Inst{7-0} = imm8;
}
// Because we have an explicit tMOVSr below, we need an alias to handle
// the immediate "movs" form here. Blech.
def : InstAlias <"movs $Rdn, $imm",
(tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>,
Requires<[IsThumb]>;
// A7-73: MOV(2) - mov setting flag.

2
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -3173,7 +3173,7 @@ unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
isARMLowRegister(Inst.getOperand(2).getReg()))
return Match_RequiresThumb2;
// Others only require ARMv6 or later.
else if (Opc == ARM::tMOVr && isThumbOne() &&
else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
isARMLowRegister(Inst.getOperand(0).getReg()) &&
isARMLowRegister(Inst.getOperand(1).getReg()))
return Match_RequiresV6;

22
test/MC/ARM/basic-thumb-instructions.s
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@ -296,3 +296,25 @@ _func:
lsrs r2, r6
@ CHECK: lsrs r2, r6 @ encoding: [0xf2,0x40]
@------------------------------------------------------------------------------
@ MOV (immediate)
@------------------------------------------------------------------------------
movs r2, #0
movs r2, #255
movs r2, #23
@ CHECK: movs r2, #0 @ encoding: [0x00,0x22]
@ CHECK: movs r2, #255 @ encoding: [0xff,0x22]
@ CHECK: movs r2, #23 @ encoding: [0x17,0x22]
@------------------------------------------------------------------------------
@ MOV (register)
@------------------------------------------------------------------------------
mov r3, r4
movs r1, r3
@ CHECK: mov r3, r4 @ encoding: [0x23,0x46]
@ CHECK: movs r1, r3 @ encoding: [0x19,0x00]

8
test/MC/ARM/thumb-diagnostics.s
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@ -1,5 +1,7 @@
@ RUN: not llvm-mc -triple=thumbv6-apple-darwin < %s 2> %t
@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
@ RUN: not llvm-mc -triple=thumbv5-apple-darwin < %s 2> %t
@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V5 < %t %s
@ Check for various assembly diagnostic messages on invalid input.
@ -15,9 +17,9 @@
@ CHECK-ERRORS: error: instruction variant requires Thumb2
@ CHECK-ERRORS: add r2, r3
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: instruction variant requires ARMv6 or later
@ CHECK-ERRORS: mov r2, r3
@ CHECK-ERRORS: ^
@ CHECK-ERRORS-V5: error: instruction variant requires ARMv6 or later
@ CHECK-ERRORS-V5: mov r2, r3
@ CHECK-ERRORS-V5: ^
@ Out of range immediates for ASR instruction.