RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-12-01 07:30:31 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

R600/SI: Add slc, glc, and tfe to non-atomic _ADDR64 instructions

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230757 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2015-02-27 14:59:41 +00:00
parent 8407da0dbc
commit 4ed3bf29cd
4 changed files with 33 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
lib/Target/R600/AMDGPUISelDAGToDAG.cpp
View File

@ -95,7 +95,8 @@ private:
SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
SDValue &TFE) const;
bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
SDValue &SOffset, SDValue &Offset) const;
SDValue &SOffset, SDValue &Offset, SDValue &GLC,
SDValue &SLC, SDValue &TFE) const;
bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
SDValue &VAddr, SDValue &SOffset, SDValue &Offset,
SDValue &SLC) const;
@ -966,8 +967,9 @@ void AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
SDValue &VAddr, SDValue &SOffset,
SDValue &Offset) const {
SDValue Ptr, Offen, Idxen, Addr64, GLC, SLC, TFE;
SDValue &Offset, SDValue &GLC,
SDValue &SLC, SDValue &TFE) const {
SDValue Ptr, Offen, Idxen, Addr64;
SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
GLC, SLC, TFE);
@ -991,8 +993,9 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
SDValue &Offset,
SDValue &SLC) const {
SLC = CurDAG->getTargetConstant(0, MVT::i1);
SDValue GLC, TFE;
return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset);
return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset, GLC, SLC, TFE);
}
bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,

8
lib/Target/R600/SIInstrInfo.cpp
View File

@ -1870,7 +1870,10 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
// This will be replaced later
// with the new value of vaddr.
.addOperand(*SOffset)
.addOperand(*Offset);
.addOperand(*Offset)
.addImm(0) // glc
.addImm(0) // slc
.addImm(0); // tfe
MI->removeFromParent();
MI = Addr64;
@ -2050,6 +2053,9 @@ void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) con
MI->getOperand(1).setReg(SRsrc);
MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0));
MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // glc
MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // slc
MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // tfe
const TargetRegisterClass *NewDstRC =
RI.getRegClass(get(NewOpcode).OpInfo[0].RegClass);

26
lib/Target/R600/SIInstrInfo.td
View File

@ -292,7 +292,7 @@ def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
def MUBUFAddr64 : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
@ -1941,14 +1941,17 @@ multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
}
let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0 in {
let offen = 0, idxen = 0 in {
defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
(ins SReg_128:$srsrc, VReg_64:$vaddr,
SCSrc_32:$soffset, mbuf_offset:$offset),
name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset",
SCSrc_32:$soffset, mbuf_offset:$offset,
glc:$glc, slc:$slc, tfe:$tfe),
name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
"$glc"#"$slc"#"$tfe",
[(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
i64:$vaddr, i32:$soffset,
i16:$offset)))]>;
i16:$offset, i1:$glc, i1:$slc,
i1:$tfe)))]>;
}
}
}
@ -1961,7 +1964,7 @@ multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
tfe:$tfe),
name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
"$glc"#"$slc"#"$tfe", []>;
"$glc"#"$slc"#"$tfe", []>;
let offen = 0, idxen = 0, vaddr = 0 in {
defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
@ -1980,15 +1983,18 @@ multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
"$glc"#"$slc"#"$tfe", []>;
} // end offen = 1, idxen = 0
let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0 in {
let offen = 0, idxen = 0 in {
defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
(ins vdataClass:$vdata, SReg_128:$srsrc,
VReg_64:$vaddr, SCSrc_32:$soffset,
mbuf_offset:$offset),
name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset",
mbuf_offset:$offset, glc:$glc, slc:$slc,
tfe:$tfe),
name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
"$offset"#"$glc"#"$slc"#"$tfe",
[(st store_vt:$vdata,
(MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
i32:$soffset, i16:$offset))]>;
i32:$soffset, i16:$offset,
i1:$glc, i1:$slc, i1:$tfe))]>;
}
} // End mayLoad = 0, mayStore = 1
}

5
lib/Target/R600/SIInstructions.td
View File

@ -2898,8 +2898,9 @@ def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, atomic_cmp_swap_64_local>;
multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
PatFrag constant_ld> {
def : Pat <
(vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset))),
(Instr_ADDR64 $srsrc, $vaddr, $soffset, $offset)
(vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
i16:$offset, i1:$glc, i1:$slc, i1:$tfe))),
(Instr_ADDR64 $srsrc, $vaddr, $soffset, $offset, $glc, $slc, $tfe)
>;
}