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[Hexagon] Fixes for new-value jump formation
- Recognize C2_cmpgtui, S2_tstbit_i, and S4_ntstbit_i. - Avoid creating new-value instructions with both source operands equal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279286 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek
parent
8d29e44d95
commit
4ef1afc7ce
@ -180,7 +180,7 @@ static bool commonChecksToProhibitNewValueJump(bool afterRA,
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return false;
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// if call in path, bail out.
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if (MII->getOpcode() == Hexagon::J2_call)
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if (MII->isCall())
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return false;
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// if NVJ is running prior to RA, do the following checks.
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@ -189,9 +189,9 @@ static bool commonChecksToProhibitNewValueJump(bool afterRA,
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// to new value jump. If they are in the path, bail out.
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// KILL sets kill flag on the opcode. It also sets up a
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// single register, out of pair.
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// %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
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// %D0<def> = S2_lsr_r_p %D0<kill>, %R2<kill>
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// %R0<def> = KILL %R0, %D0<imp-use,kill>
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// %P0<def> = CMPEQri %R0<kill>, 0
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// %P0<def> = C2_cmpeqi %R0<kill>, 0
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// PHI can be anything after RA.
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// COPY can remateriaze things in between feeder, compare and nvj.
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if (MII->getOpcode() == TargetOpcode::KILL ||
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@ -203,7 +203,7 @@ static bool commonChecksToProhibitNewValueJump(bool afterRA,
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// of registers by individual passes in the backend. At this time,
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// we don't know the scope of usage and definitions of these
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// instructions.
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if (MII->getOpcode() == Hexagon::LDriw_pred ||
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if (MII->getOpcode() == Hexagon::LDriw_pred ||
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MII->getOpcode() == Hexagon::STriw_pred)
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return false;
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}
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@ -226,10 +226,23 @@ static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
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// range specified by the arch.
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if (!secondReg) {
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int64_t v = MI.getOperand(2).getImm();
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bool Valid = false;
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if (!(isUInt<5>(v) || ((MI.getOpcode() == Hexagon::C2_cmpeqi ||
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MI.getOpcode() == Hexagon::C2_cmpgti) &&
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(v == -1))))
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switch (MI.getOpcode()) {
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case Hexagon::C2_cmpeqi:
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case Hexagon::C2_cmpgti:
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Valid = (isUInt<5>(v) || v == -1);
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break;
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case Hexagon::C2_cmpgtui:
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Valid = isUInt<5>(v);
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break;
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case Hexagon::S2_tstbit_i:
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case Hexagon::S4_ntstbit_i:
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Valid = (v == 0);
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break;
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}
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if (!Valid)
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return false;
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}
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@ -239,6 +252,11 @@ static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
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if (secondReg) {
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cmpOp2 = MI.getOperand(2).getReg();
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// If the same register appears as both operands, we cannot generate a new
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// value compare. Only one operand may use the .new suffix.
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if (cmpReg1 == cmpOp2)
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return false;
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// Make sure that that second register is not from COPY
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// At machine code level, we don't need this, but if we decide
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// to move new value jump prior to RA, we would be needing this.
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@ -255,6 +273,8 @@ static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
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++II ;
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for (MachineBasicBlock::iterator localII = II; localII != end;
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++localII) {
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if (localII->isDebugValue())
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continue;
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// Check 1.
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// If "common" checks fail, bail out.
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@ -474,7 +494,7 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
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//if(LVs.isLiveOut(predReg, *MBB)) break;
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// Get all the successors of this block - which will always
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// be 2. Check if the predicate register is live in in those
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// be 2. Check if the predicate register is live-in in those
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// successor. If yes, we can not delete the predicate -
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// I am doing this only because LLVM does not provide LiveOut
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// at the BB level.
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@ -582,8 +602,9 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
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if (isSecondOpReg) {
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// In case of CMPLT, or CMPLTU, or EQ with the second register
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// to newify, swap the operands.
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if (cmpInstr->getOpcode() == Hexagon::C2_cmpeq &&
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feederReg == (unsigned) cmpOp2) {
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unsigned COp = cmpInstr->getOpcode();
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if ((COp == Hexagon::C2_cmpeq || COp == Hexagon::C4_cmpneq) &&
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(feederReg == (unsigned) cmpOp2)) {
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unsigned tmp = cmpReg1;
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bool tmpIsKill = MO1IsKill;
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cmpReg1 = cmpOp2;
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63
test/CodeGen/Hexagon/newvalueSameReg.ll
Normal file
63
test/CodeGen/Hexagon/newvalueSameReg.ll
Normal file
@ -0,0 +1,63 @@
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; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s
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;
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; Expand-condsets eliminates the "mux" instruction, which is what this
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; testcase is checking.
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%struct._Dnk_filet.1 = type { i16, i8, i32, i8*, i8*, i8*, i8*, i8*, i8*, i32*, [2 x i32], i8*, i8*, i8*, %struct._Mbstatet.0, i8*, [8 x i8], i8 }
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%struct._Mbstatet.0 = type { i32, i16, i16 }
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@_Stdout = external global %struct._Dnk_filet.1
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@.str = external unnamed_addr constant [23 x i8], align 8
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; Test that we don't generate a new value compare if the operands are
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; the same register.
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; CHECK-NOT: cmp.eq([[REG0:(r[0-9]+)]].new, [[REG0]])
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; CHECK: cmp.eq([[REG1:(r[0-9]+)]], [[REG1]])
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; Function Attrs: nounwind
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declare void @fprintf(%struct._Dnk_filet.1* nocapture, i8* nocapture readonly, ...) #1
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define void @main() #0 {
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entry:
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%0 = load i32*, i32** undef, align 4
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%1 = load i32, i32* undef, align 4
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br i1 undef, label %if.end, label %_ZNSt6vectorIbSaIbEE3endEv.exit
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_ZNSt6vectorIbSaIbEE3endEv.exit:
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%2 = icmp slt i32 %1, 0
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%sub5.i.i.i = lshr i32 %1, 5
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%add619.i.i.i = add i32 %sub5.i.i.i, -134217728
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%sub5.i.pn.i.i = select i1 %2, i32 %add619.i.i.i, i32 %sub5.i.i.i
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%storemerge2.i.i = getelementptr inbounds i32, i32* %0, i32 %sub5.i.pn.i.i
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%cmp.i.i = icmp ult i32* %storemerge2.i.i, %0
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%.mux = select i1 %cmp.i.i, i32 0, i32 1
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br i1 undef, label %_ZNSt6vectorIbSaIbEE3endEv.exit57, label %if.end
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_ZNSt6vectorIbSaIbEE3endEv.exit57:
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%3 = icmp slt i32 %1, 0
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%sub5.i.i.i44 = lshr i32 %1, 5
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%add619.i.i.i45 = add i32 %sub5.i.i.i44, -134217728
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%sub5.i.pn.i.i46 = select i1 %3, i32 %add619.i.i.i45, i32 %sub5.i.i.i44
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%storemerge2.i.i47 = getelementptr inbounds i32, i32* %0, i32 %sub5.i.pn.i.i46
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%cmp.i38 = icmp ult i32* %storemerge2.i.i47, %0
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%.reg2mem.sroa.0.sroa.0.0.load14.i.reload = select i1 %cmp.i38, i32 0, i32 1
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%cmp = icmp eq i32 %.mux, %.reg2mem.sroa.0.sroa.0.0.load14.i.reload
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br i1 %cmp, label %if.end, label %if.then
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if.then:
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call void (%struct._Dnk_filet.1*, i8*, ...) @fprintf(%struct._Dnk_filet.1* @_Stdout, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @.str, i32 0, i32 0), i32 %.mux, i32 %.reg2mem.sroa.0.sroa.0.0.load14.i.reload) #1
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unreachable
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if.end:
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br i1 undef, label %_ZNSt6vectorIbSaIbEED2Ev.exit, label %if.then.i.i.i
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if.then.i.i.i:
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unreachable
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_ZNSt6vectorIbSaIbEED2Ev.exit:
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ret void
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}
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attributes #0 = { "target-cpu"="hexagonv5" }
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attributes #1 = { nounwind "target-cpu"="hexagonv5" }
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