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[Power9] Implement new altivec instructions: permute, count zero, extend sign, negate, parity, shift/rotate, mul10
This change implements the following vector operations: - vclzlsbb vctzlsbb vctzb vctzd vctzh vctzw - vextsb2w vextsh2w vextsb2d vextsh2d vextsw2d - vnegd vnegw - vprtybd vprtybq vprtybw - vbpermd vpermr - vrlwnm vrlwmi vrldnm vrldmi vslv vsrv - vmul10cuq vmul10uq vmul10ecuq vmul10euq 28 instructions Thanks Nemanja, Kit for invaluable hints and discussion! Reviewers: hal, nemanja, kbarton, tjablin, amehsan Phabricator: http://reviews.llvm.org/D15887 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264504 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chuang-Yu Cheng
parent
5e8cf48d61
commit
4f013a7ba6
@ -1277,4 +1277,65 @@ def VINSERTB : VX1_VT5_UIM5_VB5<781, "vinsertb", []>;
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def VINSERTH : VX1_VT5_UIM5_VB5<845, "vinserth", []>;
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def VINSERTW : VX1_VT5_UIM5_VB5<909, "vinsertw", []>;
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def VINSERTD : VX1_VT5_UIM5_VB5<973, "vinsertd", []>;
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class VX_VT5_EO5_VB5<bits<11> xo, bits<5> eo, string opc, list<dag> pattern>
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: VXForm_RD5_XO5_RS5<xo, eo, (outs vrrc:$vD), (ins vrrc:$vB),
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!strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>;
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// Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD]
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def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs g8rc:$rD), (ins vrrc:$vB),
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"vclzlsbb $rD, $vB", IIC_VecGeneral, []>;
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def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs g8rc:$rD), (ins vrrc:$vB),
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"vctzlsbb $rD, $vB", IIC_VecGeneral, []>;
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// Vector Count Trailing Zeros
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def VCTZB : VX_VT5_EO5_VB5<1538, 28, "vctzb", []>;
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def VCTZH : VX_VT5_EO5_VB5<1538, 29, "vctzh", []>;
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def VCTZW : VX_VT5_EO5_VB5<1538, 30, "vctzw", []>;
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def VCTZD : VX_VT5_EO5_VB5<1538, 31, "vctzd", []>;
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// Vector Extend Sign
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def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w", []>;
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def VEXTSH2W : VX_VT5_EO5_VB5<1538, 17, "vextsh2w", []>;
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def VEXTSB2D : VX_VT5_EO5_VB5<1538, 24, "vextsb2d", []>;
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def VEXTSH2D : VX_VT5_EO5_VB5<1538, 25, "vextsh2d", []>;
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def VEXTSW2D : VX_VT5_EO5_VB5<1538, 26, "vextsw2d", []>;
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// Vector Integer Negate
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def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw", []>;
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def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd", []>;
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// Vector Parity Byte
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def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", []>;
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def VPRTYBD : VX_VT5_EO5_VB5<1538, 9, "vprtybd", []>;
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def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", []>;
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// Vector (Bit) Permute (Right-indexed)
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def VBPERMD : VXForm_1<1484, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vbpermd $vD, $vA, $vB", IIC_VecFP, []>;
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def VPERMR : VAForm_1a<59, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
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"vpermr $vD, $vA, $vB, $vC", IIC_VecFP, []>;
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class VX1_VT5_VA5_VB5<bits<11> xo, string opc, list<dag> pattern>
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: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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!strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern>;
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// Vector Rotate Left Mask/Mask-Insert
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def VRLWNM : VX1_VT5_VA5_VB5<389, "vrlwnm", []>;
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def VRLWMI : VX1_VT5_VA5_VB5<133, "vrlwmi", []>;
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def VRLDNM : VX1_VT5_VA5_VB5<453, "vrldnm", []>;
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def VRLDMI : VX1_VT5_VA5_VB5<197, "vrldmi", []>;
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// Vector Shift Left/Right
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def VSLV : VX1_VT5_VA5_VB5<1860, "vslv", []>;
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def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv", []>;
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// Vector Multiply-by-10 (& Write Carry) Unsigned Quadword
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def VMUL10UQ : VXForm_BX<513, (outs vrrc:$vD), (ins vrrc:$vA),
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"vmul10uq $vD, $vA", IIC_VecFP, []>;
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def VMUL10CUQ : VXForm_BX< 1, (outs vrrc:$vD), (ins vrrc:$vA),
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"vmul10cuq $vD, $vA", IIC_VecFP, []>;
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// Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword
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def VMUL10EUQ : VX1_VT5_VA5_VB5<577, "vmul10euq" , []>;
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def VMUL10ECUQ : VX1_VT5_VA5_VB5< 65, "vmul10ecuq", []>;
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} // end HasP9Altivec
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@ -1609,6 +1609,21 @@ class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
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let Inst{21-31} = xo;
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}
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// e.g. [PO VRT EO VRB XO]
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class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL,
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string asmstr, InstrItinClass itin, list<dag> pattern>
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: I<4, OOL, IOL, asmstr, itin> {
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bits<5> RD;
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bits<5> VB;
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let Pattern = pattern;
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let Inst{6-10} = RD;
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let Inst{11-15} = eo;
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let Inst{16-20} = VB;
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let Inst{21-31} = xo;
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}
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/// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX"
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class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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@ -35,6 +35,111 @@ Altivec:
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(set v4i32:$vD, (int_ppc_altivec_vinserth v4i32:$vA, imm:$UIMM))
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(set v2i64:$vD, (int_ppc_altivec_vinsertw v2i64:$vA, imm:$UIMM))
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- Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD]:
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vclzlsbb vctzlsbb
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. Use intrinsic:
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(set i64:$rD, (int_ppc_altivec_vclzlsbb v16i8:$vB))
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(set i64:$rD, (int_ppc_altivec_vctzlsbb v16i8:$vB))
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- Vector Count Trailing Zeros: vctzb vctzh vctzw vctzd
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. Map to llvm cttz
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(set v16i8:$vD, (cttz v16i8:$vB)) // vctzb
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(set v8i16:$vD, (cttz v8i16:$vB)) // vctzh
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(set v4i32:$vD, (cttz v4i32:$vB)) // vctzw
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(set v2i64:$vD, (cttz v2i64:$vB)) // vctzd
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- Vector Extend Sign: vextsb2w vextsh2w vextsb2d vextsh2d vextsw2d
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. vextsb2w:
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(set v4i32:$vD, (sext v4i8:$vB))
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// PowerISA_V3.0:
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do i = 0 to 3
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VR[VRT].word[i] ← EXTS32(VR[VRB].word[i].byte[3])
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end
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. vextsh2w:
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(set v4i32:$vD, (sext v4i16:$vB))
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// PowerISA_V3.0:
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do i = 0 to 3
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VR[VRT].word[i] ← EXTS32(VR[VRB].word[i].hword[1])
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end
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. vextsb2d
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(set v2i64:$vD, (sext v2i8:$vB))
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// PowerISA_V3.0:
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do i = 0 to 1
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VR[VRT].dword[i] ← EXTS64(VR[VRB].dword[i].byte[7])
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end
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. vextsh2d
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(set v2i64:$vD, (sext v2i16:$vB))
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// PowerISA_V3.0:
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do i = 0 to 1
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VR[VRT].dword[i] ← EXTS64(VR[VRB].dword[i].hword[3])
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end
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. vextsw2d
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(set v2i64:$vD, (sext v2i32:$vB))
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// PowerISA_V3.0:
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do i = 0 to 1
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VR[VRT].dword[i] ← EXTS64(VR[VRB].dword[i].word[1])
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end
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- Vector Integer Negate: vnegw vnegd
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. Map to llvm ineg
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(set v4i32:$rT, (ineg v4i32:$rA)) // vnegw
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(set v2i64:$rT, (ineg v2i64:$rA)) // vnegd
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- Vector Parity Byte: vprtybw vprtybd vprtybq
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. Use intrinsic:
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(set v4i32:$rD, (int_ppc_altivec_vprtybw v4i32:$vB))
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(set v2i64:$rD, (int_ppc_altivec_vprtybd v2i64:$vB))
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(set v1i128:$rD, (int_ppc_altivec_vprtybq v1i128:$vB))
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- Vector (Bit) Permute (Right-indexed):
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. vbpermd: Same as "vbpermq", use VX1_Int_Ty2:
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VX1_Int_Ty2<1484, "vbpermd", int_ppc_altivec_vbpermd, v2i64, v2i64>;
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. vpermr: use VA1a_Int_Ty3
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VA1a_Int_Ty3<59, "vpermr", int_ppc_altivec_vpermr, v16i8, v16i8, v16i8>;
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- Vector Rotate Left Mask/Mask-Insert: vrlwnm vrlwmi vrldnm vrldmi
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. Use intrinsic:
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VX1_Int_Ty<389, "vrlwnm", int_ppc_altivec_vrlwnm, v4i32>;
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VX1_Int_Ty<133, "vrlwmi", int_ppc_altivec_vrlwmi, v4i32>;
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VX1_Int_Ty<453, "vrldnm", int_ppc_altivec_vrldnm, v2i64>;
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VX1_Int_Ty<197, "vrldmi", int_ppc_altivec_vrldmi, v2i64>;
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- Vector Shift Left/Right: vslv vsrv
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. Use intrinsic, don't map to llvm shl and lshr, because they have different
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semantics, e.g. vslv:
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do i = 0 to 15
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sh ← VR[VRB].byte[i].bit[5:7]
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VR[VRT].byte[i] ← src.byte[i:i+1].bit[sh:sh+7]
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end
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VR[VRT].byte[i] is composed of 2 bytes from src.byte[i:i+1]
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. VX1_Int_Ty<1860, "vslv", int_ppc_altivec_vslv, v16i8>;
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VX1_Int_Ty<1796, "vsrv", int_ppc_altivec_vsrv, v16i8>;
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- Vector Multiply-by-10 (& Write Carry) Unsigned Quadword:
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vmul10uq vmul10cuq
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. Use intrinsic:
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VX1_Int_Ty<513, "vmul10uq", int_ppc_altivec_vmul10uq, v1i128>;
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VX1_Int_Ty< 1, "vmul10cuq", int_ppc_altivec_vmul10cuq, v1i128>;
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- Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword:
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vmul10euq vmul10ecuq
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. Use intrinsic:
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VX1_Int_Ty<577, "vmul10euq", int_ppc_altivec_vmul10euq, v1i128>;
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VX1_Int_Ty< 65, "vmul10ecuq", int_ppc_altivec_vmul10ecuq, v1i128>;
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VSX:
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- QP Compare Ordered/Unordered: xscmpoqp xscmpuqp
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@ -752,3 +752,88 @@
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# CHECK: vinsertd 2, 3, 8
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0x10 0x48 0x1b 0xcd
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# Power9 instructions
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# CHECK: vclzlsbb 2, 3
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0x10 0x40 0x1e 0x02
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# CHECK: vctzlsbb 2, 3
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0x10 0x41 0x1e 0x02
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# CHECK: vctzb 2, 3
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0x10 0x5c 0x1e 0x02
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# CHECK: vctzh 2, 3
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0x10 0x5d 0x1e 0x02
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# CHECK: vctzw 2, 3
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0x10 0x5e 0x1e 0x02
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# CHECK: vctzd 2, 3
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0x10 0x5f 0x1e 0x02
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# CHECK: vextsb2w 2, 3
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0x10 0x50 0x1e 0x02
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# CHECK: vextsh2w 2, 3
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0x10 0x51 0x1e 0x02
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# CHECK: vextsb2d 2, 3
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0x10 0x58 0x1e 0x02
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# CHECK: vextsh2d 2, 3
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0x10 0x59 0x1e 0x02
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# CHECK: vextsw2d 2, 3
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0x10 0x5a 0x1e 0x02
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# CHECK: vnegw 2, 3
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0x10 0x46 0x1e 0x02
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# CHECK: vnegd 2, 3
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0x10 0x47 0x1e 0x02
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# CHECK: vprtybw 2, 3
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0x10 0x48 0x1e 0x02
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# CHECK: vprtybd 2, 3
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0x10 0x49 0x1e 0x02
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# CHECK: vprtybq 2, 3
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0x10 0x4a 0x1e 0x02
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# CHECK: vbpermd 2, 5, 17
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0x10 0x45 0x8d 0xcc
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# CHECK: vpermr 2, 3, 4, 5
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0x10 0x43 0x21 0x7b
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# CHECK: vrlwnm 2, 3, 4
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0x10 0x43 0x21 0x85
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# CHECK: vrlwmi 2, 3, 4
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0x10 0x43 0x20 0x85
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# CHECK: vrldnm 2, 3, 4
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0x10 0x43 0x21 0xc5
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# CHECK: vrldmi 2, 3, 4
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0x10 0x43 0x20 0xc5
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# CHECK: vslv 2, 3, 4
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0x10 0x43 0x27 0x44
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# CHECK: vsrv 2, 3, 4
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0x10 0x43 0x27 0x04
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# CHECK: vmul10uq 2, 3
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0x10 0x43 0x02 0x01
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# CHECK: vmul10cuq 2, 3
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0x10 0x43 0x00 0x01
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# CHECK: vmul10euq 2, 3, 4
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0x10 0x43 0x22 0x41
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# CHECK: vmul10ecuq 2, 3, 4
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0x10 0x43 0x20 0x41
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@ -830,3 +830,105 @@
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# CHECK-LE: vinsertd 2, 3, 8 # encoding: [0xcd,0x1b,0x48,0x10]
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vinsertd 2, 3, 8
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# Power9 instructions
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# Vector Count Trailing Zeros
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# CHECK-BE: vctzb 2, 3 # encoding: [0x10,0x5c,0x1e,0x02]
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# CHECK-LE: vctzb 2, 3 # encoding: [0x02,0x1e,0x5c,0x10]
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vctzb 2, 3
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# CHECK-BE: vctzh 2, 3 # encoding: [0x10,0x5d,0x1e,0x02]
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# CHECK-LE: vctzh 2, 3 # encoding: [0x02,0x1e,0x5d,0x10]
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vctzh 2, 3
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# CHECK-BE: vctzw 2, 3 # encoding: [0x10,0x5e,0x1e,0x02]
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# CHECK-LE: vctzw 2, 3 # encoding: [0x02,0x1e,0x5e,0x10]
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vctzw 2, 3
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# CHECK-BE: vctzd 2, 3 # encoding: [0x10,0x5f,0x1e,0x02]
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# CHECK-LE: vctzd 2, 3 # encoding: [0x02,0x1e,0x5f,0x10]
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vctzd 2, 3
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# CHECK-BE: vclzlsbb 2, 3 # encoding: [0x10,0x40,0x1e,0x02]
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# CHECK-LE: vclzlsbb 2, 3 # encoding: [0x02,0x1e,0x40,0x10]
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vclzlsbb 2, 3
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# CHECK-BE: vctzlsbb 2, 3 # encoding: [0x10,0x41,0x1e,0x02]
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# CHECK-LE: vctzlsbb 2, 3 # encoding: [0x02,0x1e,0x41,0x10]
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vctzlsbb 2, 3
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# Vector Extend Sign
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# CHECK-BE: vextsb2w 2, 3 # encoding: [0x10,0x50,0x1e,0x02]
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# CHECK-LE: vextsb2w 2, 3 # encoding: [0x02,0x1e,0x50,0x10]
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vextsb2w 2, 3
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# CHECK-BE: vextsh2w 2, 3 # encoding: [0x10,0x51,0x1e,0x02]
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# CHECK-LE: vextsh2w 2, 3 # encoding: [0x02,0x1e,0x51,0x10]
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vextsh2w 2, 3
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# CHECK-BE: vextsb2d 2, 3 # encoding: [0x10,0x58,0x1e,0x02]
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# CHECK-LE: vextsb2d 2, 3 # encoding: [0x02,0x1e,0x58,0x10]
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vextsb2d 2, 3
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# CHECK-BE: vextsh2d 2, 3 # encoding: [0x10,0x59,0x1e,0x02]
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# CHECK-LE: vextsh2d 2, 3 # encoding: [0x02,0x1e,0x59,0x10]
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vextsh2d 2, 3
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# CHECK-BE: vextsw2d 2, 3 # encoding: [0x10,0x5a,0x1e,0x02]
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# CHECK-LE: vextsw2d 2, 3 # encoding: [0x02,0x1e,0x5a,0x10]
|
||||
vextsw2d 2, 3
|
||||
|
||||
# Vector Integer Negate
|
||||
# CHECK-BE: vnegw 2, 3 # encoding: [0x10,0x46,0x1e,0x02]
|
||||
# CHECK-LE: vnegw 2, 3 # encoding: [0x02,0x1e,0x46,0x10]
|
||||
vnegw 2, 3
|
||||
# CHECK-BE: vnegd 2, 3 # encoding: [0x10,0x47,0x1e,0x02]
|
||||
# CHECK-LE: vnegd 2, 3 # encoding: [0x02,0x1e,0x47,0x10]
|
||||
vnegd 2, 3
|
||||
|
||||
# Vector Parity Byte
|
||||
# CHECK-BE: vprtybw 2, 3 # encoding: [0x10,0x48,0x1e,0x02]
|
||||
# CHECK-LE: vprtybw 2, 3 # encoding: [0x02,0x1e,0x48,0x10]
|
||||
vprtybw 2, 3
|
||||
# CHECK-BE: vprtybd 2, 3 # encoding: [0x10,0x49,0x1e,0x02]
|
||||
# CHECK-LE: vprtybd 2, 3 # encoding: [0x02,0x1e,0x49,0x10]
|
||||
vprtybd 2, 3
|
||||
# CHECK-BE: vprtybq 2, 3 # encoding: [0x10,0x4a,0x1e,0x02]
|
||||
# CHECK-LE: vprtybq 2, 3 # encoding: [0x02,0x1e,0x4a,0x10]
|
||||
vprtybq 2, 3
|
||||
|
||||
# Vector (Bit) Permute (Right-indexed)
|
||||
# CHECK-BE: vbpermd 2, 5, 17 # encoding: [0x10,0x45,0x8d,0xcc]
|
||||
# CHECK-LE: vbpermd 2, 5, 17 # encoding: [0xcc,0x8d,0x45,0x10]
|
||||
vbpermd 2, 5, 17
|
||||
# CHECK-BE: vpermr 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x7b]
|
||||
# CHECK-LE: vpermr 2, 3, 4, 5 # encoding: [0x7b,0x21,0x43,0x10]
|
||||
vpermr 2, 3, 4, 5
|
||||
|
||||
# Vector Rotate Left Mask/Mask-Insert
|
||||
# CHECK-BE: vrlwnm 2, 3, 4 # encoding: [0x10,0x43,0x21,0x85]
|
||||
# CHECK-LE: vrlwnm 2, 3, 4 # encoding: [0x85,0x21,0x43,0x10]
|
||||
vrlwnm 2, 3, 4
|
||||
# CHECK-BE: vrlwmi 2, 3, 4 # encoding: [0x10,0x43,0x20,0x85]
|
||||
# CHECK-LE: vrlwmi 2, 3, 4 # encoding: [0x85,0x20,0x43,0x10]
|
||||
vrlwmi 2, 3, 4
|
||||
# CHECK-BE: vrldnm 2, 3, 4 # encoding: [0x10,0x43,0x21,0xc5]
|
||||
# CHECK-LE: vrldnm 2, 3, 4 # encoding: [0xc5,0x21,0x43,0x10]
|
||||
vrldnm 2, 3, 4
|
||||
# CHECK-BE: vrldmi 2, 3, 4 # encoding: [0x10,0x43,0x20,0xc5]
|
||||
# CHECK-LE: vrldmi 2, 3, 4 # encoding: [0xc5,0x20,0x43,0x10]
|
||||
vrldmi 2, 3, 4
|
||||
|
||||
# Vector Shift Left/Right
|
||||
# CHECK-BE: vslv 2, 3, 4 # encoding: [0x10,0x43,0x27,0x44]
|
||||
# CHECK-LE: vslv 2, 3, 4 # encoding: [0x44,0x27,0x43,0x10]
|
||||
vslv 2, 3, 4
|
||||
# CHECK-BE: vsrv 2, 3, 4 # encoding: [0x10,0x43,0x27,0x04]
|
||||
# CHECK-LE: vsrv 2, 3, 4 # encoding: [0x04,0x27,0x43,0x10]
|
||||
vsrv 2, 3, 4
|
||||
|
||||
# Vector Multiply-by-10
|
||||
# CHECK-BE: vmul10uq 2, 3 # encoding: [0x10,0x43,0x02,0x01]
|
||||
# CHECK-LE: vmul10uq 2, 3 # encoding: [0x01,0x02,0x43,0x10]
|
||||
vmul10uq 2, 3
|
||||
# CHECK-BE: vmul10cuq 2, 3 # encoding: [0x10,0x43,0x00,0x01]
|
||||
# CHECK-LE: vmul10cuq 2, 3 # encoding: [0x01,0x00,0x43,0x10]
|
||||
vmul10cuq 2, 3
|
||||
# CHECK-BE: vmul10euq 2, 3, 4 # encoding: [0x10,0x43,0x22,0x41]
|
||||
# CHECK-LE: vmul10euq 2, 3, 4 # encoding: [0x41,0x22,0x43,0x10]
|
||||
vmul10euq 2, 3, 4
|
||||
# CHECK-BE: vmul10ecuq 2, 3, 4 # encoding: [0x10,0x43,0x20,0x41]
|
||||
# CHECK-LE: vmul10ecuq 2, 3, 4 # encoding: [0x41,0x20,0x43,0x10]
|
||||
vmul10ecuq 2, 3, 4
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user