RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2025-02-19 04:29:45 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[ARM GlobalISel] Remove hand-written G_FADD selection

Browse Source 
Remove the code selecting G_FADD - now that TableGen can handle more
opcodes, it's not needed anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302511 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Diana Picus 2017-05-09 08:32:42 +00:00
parent b23f8ea900
commit 4f0f7c08bf
1 changed files with 0 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
lib/Target/ARM/ARMInstructionSelector.cpp
View File

@ -135,28 +135,6 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
return true;
}
static bool selectFAdd(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII,
MachineRegisterInfo &MRI) {
assert(TII.getSubtarget().hasVFP2() && "Can't select fp add without vfp");
LLT Ty = MRI.getType(MIB->getOperand(0).getReg());
unsigned ValSize = Ty.getSizeInBits();
if (ValSize == 32) {
if (TII.getSubtarget().useNEONForSinglePrecisionFP())
return false;
MIB->setDesc(TII.get(ARM::VADDS));
} else {
assert(ValSize == 64 && "Unsupported size for floating point value");
if (TII.getSubtarget().isFPOnlySP())
return false;
MIB->setDesc(TII.get(ARM::VADDD));
}
MIB.add(predOps(ARMCC::AL));
return true;
}
static bool selectSequence(MachineInstrBuilder &MIB,
const ARMBaseInstrInfo &TII,
MachineRegisterInfo &MRI,
@ -393,10 +371,6 @@ bool ARMInstructionSelector::select(MachineInstr &I) const {
}
MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
break;
case G_FADD:
if (!selectFAdd(MIB, TII, MRI))
return false;
break;
case G_FRAME_INDEX:
// Add 0 to the given frame index and hope it will eventually be folded into
// the user(s).