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https://github.com/RPCSX/llvm.git
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- Added some SSE2 128-bit packed integer ops.
- Added SSE2 128-bit integer pack with signed saturation ops. - Added pshufhw and pshuflw ops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27252 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
75658b96bf
commit
506d3dfa90
@ -1399,10 +1399,67 @@ bool X86::isPSHUFDMask(SDNode *N) {
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return false;
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// Check if the value doesn't reference the second vector.
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for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) {
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for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
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assert(isa<ConstantSDNode>(N->getOperand(i)) &&
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"Invalid VECTOR_SHUFFLE mask!");
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if (cast<ConstantSDNode>(N->getOperand(i))->getValue() >= 4) return false;
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if (cast<ConstantSDNode>(N->getOperand(i))->getValue() >= 4)
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return false;
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}
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return true;
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}
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/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool X86::isPSHUFHWMask(SDNode *N) {
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assert(N->getOpcode() == ISD::BUILD_VECTOR);
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if (N->getNumOperands() != 8)
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return false;
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// Lower quadword copied in order.
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for (unsigned i = 0; i != 4; ++i) {
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assert(isa<ConstantSDNode>(N->getOperand(i)) &&
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"Invalid VECTOR_SHUFFLE mask!");
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if (cast<ConstantSDNode>(N->getOperand(i))->getValue() != i)
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return false;
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}
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// Upper quadword shuffled.
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for (unsigned i = 4; i != 8; ++i) {
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assert(isa<ConstantSDNode>(N->getOperand(i)) &&
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"Invalid VECTOR_SHUFFLE mask!");
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unsigned Val = cast<ConstantSDNode>(N->getOperand(i))->getValue();
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if (Val < 4 || Val > 7)
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return false;
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}
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return true;
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}
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/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool X86::isPSHUFLWMask(SDNode *N) {
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assert(N->getOpcode() == ISD::BUILD_VECTOR);
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if (N->getNumOperands() != 8)
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return false;
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// Upper quadword copied in order.
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for (unsigned i = 4; i != 8; ++i) {
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assert(isa<ConstantSDNode>(N->getOperand(i)) &&
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"Invalid VECTOR_SHUFFLE mask!");
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if (cast<ConstantSDNode>(N->getOperand(i))->getValue() != i)
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return false;
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}
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// Lower quadword shuffled.
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for (unsigned i = 0; i != 4; ++i) {
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assert(isa<ConstantSDNode>(N->getOperand(i)) &&
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"Invalid VECTOR_SHUFFLE mask!");
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unsigned Val = cast<ConstantSDNode>(N->getOperand(i))->getValue();
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if (Val > 4)
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return false;
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}
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return true;
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@ -1431,7 +1488,7 @@ bool X86::isSHUFPMask(SDNode *N) {
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// Each half must refer to only one of the vector.
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SDOperand Elt = N->getOperand(0);
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assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
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for (unsigned i = 1; i != NumElems / 2; ++i) {
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for (unsigned i = 1; i < NumElems / 2; ++i) {
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assert(isa<ConstantSDNode>(N->getOperand(i)) &&
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"Invalid VECTOR_SHUFFLE mask!");
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if (cast<ConstantSDNode>(N->getOperand(i))->getValue() !=
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@ -1440,7 +1497,7 @@ bool X86::isSHUFPMask(SDNode *N) {
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}
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Elt = N->getOperand(NumElems / 2);
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assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
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for (unsigned i = NumElems / 2; i != NumElems; ++i) {
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for (unsigned i = NumElems / 2 + 1; i < NumElems; ++i) {
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assert(isa<ConstantSDNode>(N->getOperand(i)) &&
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"Invalid VECTOR_SHUFFLE mask!");
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if (cast<ConstantSDNode>(N->getOperand(i))->getValue() !=
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@ -1583,6 +1640,40 @@ unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
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return Mask;
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}
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/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
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/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
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/// instructions.
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unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
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unsigned Mask = 0;
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// 8 nodes, but we only care about the last 4.
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for (unsigned i = 7; i >= 4; --i) {
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unsigned Val
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= cast<ConstantSDNode>(N->getOperand(i))->getValue();
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Mask |= (Val - 4);
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if (i != 4)
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Mask <<= 2;
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}
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return Mask;
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}
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/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
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/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
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/// instructions.
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unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
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unsigned Mask = 0;
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// 8 nodes, but we only care about the first 4.
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for (int i = 3; i >= 0; --i) {
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unsigned Val
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= cast<ConstantSDNode>(N->getOperand(i))->getValue();
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Mask |= Val;
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if (i != 0)
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Mask <<= 2;
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}
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return Mask;
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}
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/// NormalizeVectorShuffle - Swap vector_shuffle operands (as well as
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/// values in ther permute mask if needed. Use V1 as second vector if it is
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/// undef. Return an empty SDOperand is it is already well formed.
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@ -2399,7 +2490,10 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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// Splat && PSHUFD's 2nd vector must be undef.
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if (X86::isSplatMask(PermMask.Val) ||
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((MVT::isInteger(VT) && X86::isPSHUFDMask(PermMask.Val)))) {
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((MVT::isInteger(VT) &&
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(X86::isPSHUFDMask(PermMask.Val) ||
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X86::isPSHUFHWMask(PermMask.Val) ||
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X86::isPSHUFLWMask(PermMask.Val))))) {
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if (V2.getOpcode() != ISD::UNDEF)
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
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DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
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@ -2607,6 +2701,8 @@ X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
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return (Mask.Val->getNumOperands() == 2 ||
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X86::isSplatMask(Mask.Val) ||
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X86::isPSHUFDMask(Mask.Val) ||
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X86::isPSHUFHWMask(Mask.Val) ||
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X86::isPSHUFLWMask(Mask.Val) ||
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X86::isSHUFPMask(Mask.Val) ||
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X86::isUNPCKLMask(Mask.Val) ||
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X86::isUNPCKHMask(Mask.Val));
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@ -184,6 +184,14 @@ namespace llvm {
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool isPSHUFDMask(SDNode *N);
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/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool isPSHUFHWMask(SDNode *N);
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/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool isPSHUFLWMask(SDNode *N);
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/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to SHUFP*.
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bool isSHUFPMask(SDNode *N);
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@ -212,6 +220,16 @@ namespace llvm {
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/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
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/// instructions.
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unsigned getShuffleSHUFImmediate(SDNode *N);
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/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
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/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
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/// instructions.
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unsigned getShufflePSHUFHWImmediate(SDNode *N);
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/// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
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/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
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/// instructions.
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unsigned getShufflePSHUFLWImmediate(SDNode *N);
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}
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//===----------------------------------------------------------------------===//
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@ -45,6 +45,8 @@ def loadv8i16 : PatFrag<(ops node:$ptr), (v8i16 (load node:$ptr))>;
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def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
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def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
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def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
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def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
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def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
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def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
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@ -58,6 +60,18 @@ def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
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return getI8Imm(X86::getShuffleSHUFImmediate(N));
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}]>;
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// SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
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// PSHUFHW imm.
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def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
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return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
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}]>;
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// SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
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// PSHUFLW imm.
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def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
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return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
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}]>;
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def SSE_splat_mask : PatLeaf<(build_vector), [{
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return X86::isSplatMask(N);
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}], SHUFFLE_get_shuf_imm>;
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@ -82,6 +96,14 @@ def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isPSHUFDMask(N);
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}], SHUFFLE_get_shuf_imm>;
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def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isPSHUFHWMask(N);
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}], SHUFFLE_get_pshufhw_imm>;
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def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isPSHUFLWMask(N);
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}], SHUFFLE_get_pshuflw_imm>;
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def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isSHUFPMask(N);
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}], SHUFFLE_get_shuf_imm>;
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@ -935,25 +957,6 @@ def CMPPDrm : PDI<0xC2, MRMSrcMem,
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}
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// Shuffle and unpack instructions
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def PSHUFWrr : PSIi8<0x70, MRMDestReg,
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(ops VR64:$dst, VR64:$src1, i8imm:$src2),
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"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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def PSHUFWrm : PSIi8<0x70, MRMSrcMem,
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(ops VR64:$dst, i64mem:$src1, i8imm:$src2),
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"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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def PSHUFDrr : PDIi8<0x70, MRMDestReg,
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(ops VR128:$dst, VR128:$src1, i8imm:$src2),
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"pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst, (v4i32 (vector_shuffle
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VR128:$src1, (undef),
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PSHUFD_shuffle_mask:$src2)))]>;
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def PSHUFDrm : PDIi8<0x70, MRMSrcMem,
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(ops VR128:$dst, i128mem:$src1, i8imm:$src2),
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"pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst, (v4i32 (vector_shuffle
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(load addr:$src1), (undef),
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PSHUFD_shuffle_mask:$src2)))]>;
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let isTwoAddress = 1 in {
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def SHUFPSrr : PSIi8<0xC6, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
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@ -1081,6 +1084,10 @@ def PADDWrr : PDI<0xFD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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def PADDDrr : PDI<0xFE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"paddd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v4i32 (add VR128:$src1, VR128:$src2)))]>;
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def PADDQrr : PDI<0xD4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"paddq {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v2i64 (add VR128:$src1, VR128:$src2)))]>;
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}
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def PADDBrm : PDI<0xFC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"paddb {$src2, $dst|$dst, $src2}",
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@ -1094,6 +1101,10 @@ def PADDDrm : PDI<0xFE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"paddd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v4i32 (add VR128:$src1,
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(load addr:$src2))))]>;
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def PADDQrm : PDI<0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"paddd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v2i64 (add VR128:$src1,
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(load addr:$src2))))]>;
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def PSUBBrr : PDI<0xF8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"psubb {$src2, $dst|$dst, $src2}",
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@ -1104,6 +1115,9 @@ def PSUBWrr : PDI<0xF9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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def PSUBDrr : PDI<0xFA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"psubd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v4i32 (sub VR128:$src1, VR128:$src2)))]>;
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def PSUBQrr : PDI<0xFB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"psubq {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v2i64 (sub VR128:$src1, VR128:$src2)))]>;
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def PSUBBrm : PDI<0xF8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"psubb {$src2, $dst|$dst, $src2}",
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@ -1117,8 +1131,146 @@ def PSUBDrm : PDI<0xFA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"psubd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v4i32 (sub VR128:$src1,
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(load addr:$src2))))]>;
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def PSUBQrm : PDI<0xFB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"psubd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v2i64 (sub VR128:$src1,
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(load addr:$src2))))]>;
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}
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// Unpack and interleave
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// Logical
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let isTwoAddress = 1 in {
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let isCommutable = 1 in {
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def PANDrr : PDI<0xDB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"pand {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
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def PANDrm : PDI<0xDB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
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"pand {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v2i64 (and VR128:$src1,
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(load addr:$src2))))]>;
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def PORrr : PDI<0xDB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"por {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
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def PORrm : PDI<0xDB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
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"por {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v2i64 (or VR128:$src1,
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(load addr:$src2))))]>;
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def PXORrr : PDI<0xEF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"pxor {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
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def PXORrm : PDI<0xEF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
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"pxor {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v2i64 (xor VR128:$src1,
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(load addr:$src2))))]>;
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}
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def PANDNrr : PDI<0xDF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"pandn {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
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VR128:$src2)))]>;
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def PANDNrm : PDI<0xDF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
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"pandn {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
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(load addr:$src2))))]>;
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}
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// Pack instructions
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let isTwoAddress = 1 in {
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def PACKSSWBrr : PDI<0x63, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
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VR128:$src2),
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"packsswb {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v16i8 (int_x86_sse2_packsswb_128
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(v8i16 VR128:$src1),
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(v8i16 VR128:$src2))))]>;
|
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def PACKSSWBrm : PDI<0x63, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
|
||||
i128mem:$src2),
|
||||
"packsswb {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v16i8 (int_x86_sse2_packsswb_128
|
||||
(v8i16 VR128:$src1),
|
||||
(loadv8i16 addr:$src2))))]>;
|
||||
def PACKSSDWrr : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
|
||||
VR128:$src2),
|
||||
"packsswb {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v8i16 (int_x86_sse2_packssdw_128
|
||||
(v4i32 VR128:$src1),
|
||||
(v4i32 VR128:$src2))))]>;
|
||||
def PACKSSDWrm : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
|
||||
i128mem:$src2),
|
||||
"packsswb {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v8i16 (int_x86_sse2_packssdw_128
|
||||
(v4i32 VR128:$src1),
|
||||
(loadv4i32 addr:$src2))))]>;
|
||||
def PACKUSWBrr : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
|
||||
VR128:$src2),
|
||||
"packuswb {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v16i8 (int_x86_sse2_packuswb_128
|
||||
(v8i16 VR128:$src1),
|
||||
(v8i16 VR128:$src2))))]>;
|
||||
def PACKUSWBrm : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
|
||||
i128mem:$src2),
|
||||
"packuswb {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (v16i8 (int_x86_sse2_packuswb_128
|
||||
(v8i16 VR128:$src1),
|
||||
(loadv8i16 addr:$src2))))]>;
|
||||
}
|
||||
|
||||
// Shuffle and unpack instructions
|
||||
def PSHUFWrr : PSIi8<0x70, MRMDestReg,
|
||||
(ops VR64:$dst, VR64:$src1, i8imm:$src2),
|
||||
"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
|
||||
def PSHUFWrm : PSIi8<0x70, MRMSrcMem,
|
||||
(ops VR64:$dst, i64mem:$src1, i8imm:$src2),
|
||||
"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
|
||||
|
||||
def PSHUFDrr : PDIi8<0x70, MRMDestReg,
|
||||
(ops VR128:$dst, VR128:$src1, i8imm:$src2),
|
||||
"pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
[(set VR128:$dst, (v4i32 (vector_shuffle
|
||||
VR128:$src1, (undef),
|
||||
PSHUFD_shuffle_mask:$src2)))]>;
|
||||
def PSHUFDrm : PDIi8<0x70, MRMSrcMem,
|
||||
(ops VR128:$dst, i128mem:$src1, i8imm:$src2),
|
||||
"pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
[(set VR128:$dst, (v4i32 (vector_shuffle
|
||||
(load addr:$src1), (undef),
|
||||
PSHUFD_shuffle_mask:$src2)))]>;
|
||||
|
||||
// SSE2 with ImmT == Imm8 and XS prefix.
|
||||
def PSHUFHWrr : Ii8<0x70, MRMDestReg,
|
||||
(ops VR128:$dst, VR128:$src1, i8imm:$src2),
|
||||
"pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
[(set VR128:$dst, (v8i16 (vector_shuffle
|
||||
VR128:$src1, (undef),
|
||||
PSHUFHW_shuffle_mask:$src2)))]>,
|
||||
XS, Requires<[HasSSE2]>;
|
||||
def PSHUFHWrm : Ii8<0x70, MRMDestMem,
|
||||
(ops VR128:$dst, i128mem:$src1, i8imm:$src2),
|
||||
"pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
[(set VR128:$dst, (v8i16 (vector_shuffle
|
||||
(bc_v8i16 (loadv2i64 addr:$src1)), (undef),
|
||||
PSHUFHW_shuffle_mask:$src2)))]>,
|
||||
XS, Requires<[HasSSE2]>;
|
||||
|
||||
// SSE2 with ImmT == Imm8 and XD prefix.
|
||||
def PSHUFLWrr : Ii8<0x70, MRMDestReg,
|
||||
(ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
|
||||
"pshufLw {$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
[(set VR128:$dst, (v8i16 (vector_shuffle
|
||||
VR128:$src1, (undef),
|
||||
PSHUFLW_shuffle_mask:$src2)))]>,
|
||||
XD, Requires<[HasSSE2]>;
|
||||
def PSHUFLWrm : Ii8<0x70, MRMDestMem,
|
||||
(ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
|
||||
"pshufLw {$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
[(set VR128:$dst, (v8i16 (vector_shuffle
|
||||
(bc_v8i16 (loadv2i64 addr:$src1)), (undef),
|
||||
PSHUFLW_shuffle_mask:$src2)))]>,
|
||||
XD, Requires<[HasSSE2]>;
|
||||
|
||||
let isTwoAddress = 1 in {
|
||||
def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
|
||||
(ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"punpcklbw {$src2, $dst|$dst, $src2}",
|
||||
@ -1355,6 +1507,29 @@ def : Pat<(v16i8 (X86s2vec R32:$src)), (MOVD128rr R32:$src)>,
|
||||
// bit_convert
|
||||
def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>,
|
||||
Requires<[HasSSE2]>;
|
||||
def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>,
|
||||
Requires<[HasSSE2]>;
|
||||
def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>,
|
||||
Requires<[HasSSE2]>;
|
||||
def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
|
||||
Requires<[HasSSE2]>;
|
||||
def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>,
|
||||
Requires<[HasSSE2]>;
|
||||
def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>,
|
||||
Requires<[HasSSE2]>;
|
||||
def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
|
||||
Requires<[HasSSE2]>;
|
||||
def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src)>,
|
||||
Requires<[HasSSE2]>;
|
||||
def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>,
|
||||
Requires<[HasSSE2]>;
|
||||
def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
|
||||
Requires<[HasSSE2]>;
|
||||
def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src)>,
|
||||
Requires<[HasSSE2]>;
|
||||
def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>,
|
||||
Requires<[HasSSE2]>;
|
||||
|
||||
def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>,
|
||||
Requires<[HasSSE2]>;
|
||||
def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user