From 5081399663dc354dce6b64f0e5890802b7ac1bbc Mon Sep 17 00:00:00 2001 From: Jozef Kolek Date: Fri, 8 May 2015 14:25:11 +0000 Subject: [PATCH] [mips][microMIPSr6] Implement ALUIPC and AUIPC instructions This patch implements ALUIPC and AUIPC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8441 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236858 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MicroMips32r6InstrFormats.td | 12 ++++++++++++ lib/Target/Mips/MicroMips32r6InstrInfo.td | 16 ++++++++++++++++ lib/Target/Mips/Mips32r6InstrInfo.td | 7 ++++--- test/MC/Disassembler/Mips/micromips32r6.txt | 4 ++++ test/MC/Mips/micromips32r6/valid.s | 2 ++ 5 files changed, 38 insertions(+), 3 deletions(-) diff --git a/lib/Target/Mips/MicroMips32r6InstrFormats.td b/lib/Target/Mips/MicroMips32r6InstrFormats.td index 691eaf18766..314379d6f2f 100644 --- a/lib/Target/Mips/MicroMips32r6InstrFormats.td +++ b/lib/Target/Mips/MicroMips32r6InstrFormats.td @@ -82,3 +82,15 @@ class PCREL19_FM_MMR6 funct> : MipsR6Inst { let Inst{20-19} = funct; let Inst{18-0} = imm; } + +class PCREL16_FM_MMR6 funct> : MipsR6Inst { + bits<5> rt; + bits<16> imm; + + bits<32> Inst; + + let Inst{31-26} = 0b011110; + let Inst{25-21} = rt; + let Inst{20-16} = funct; + let Inst{15-0} = imm; +} diff --git a/lib/Target/Mips/MicroMips32r6InstrInfo.td b/lib/Target/Mips/MicroMips32r6InstrInfo.td index 304a2bb6a5a..3111835aa1a 100644 --- a/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -20,6 +20,8 @@ class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>; class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>; class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>; class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>; +class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>; +class AUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11110>; class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>; class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>; class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>; @@ -109,6 +111,17 @@ class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, list Defs = [AT]; } +class ALUIPC_MMR6_DESC_BASE + : MMR6Arch { + dag OutOperandList = (outs GPROpnd:$rt); + dag InOperandList = (ins simm16:$imm); + string AsmString = !strconcat(instr_asm, "\t$rt, $imm"); + list Pattern = []; +} + +class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>; +class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>; + class PCREL_MMR6_DESC_BASE : MMR6Arch { dag OutOperandList = (outs GPROpnd:$rt); @@ -132,6 +145,9 @@ def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6; def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6; def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC, ISA_MICROMIPS32R6; +def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC, + ISA_MICROMIPS32R6; +def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6; def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6; def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6; def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC, diff --git a/lib/Target/Mips/Mips32r6InstrInfo.td b/lib/Target/Mips/Mips32r6InstrInfo.td index 5f271eb2287..01d922b0af4 100644 --- a/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/lib/Target/Mips/Mips32r6InstrInfo.td @@ -264,7 +264,8 @@ class ALIGN_DESC_BASE; -class ALUIPC_DESC_BASE { +class ALUIPC_DESC_BASE + : MipsR6Arch { dag OutOperandList = (outs GPROpnd:$rs); dag InOperandList = (ins simm16:$imm); string AsmString = !strconcat(instr_asm, "\t$rs, $imm"); @@ -647,9 +648,9 @@ class SDBBP_R6_DESC { def ADDIUPC : R6MMR6Rel, ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6; def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6; -def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6; +def ALUIPC : R6MMR6Rel, ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6; def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6; -def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6; +def AUIPC : R6MMR6Rel, AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6; def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6; def BALC : R6MMR6Rel, BALC_ENC, BALC_DESC, ISA_MIPS32R6; def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6, HARDFLOAT; diff --git a/test/MC/Disassembler/Mips/micromips32r6.txt b/test/MC/Disassembler/Mips/micromips32r6.txt index 17332375a90..0d840e4a4ea 100644 --- a/test/MC/Disassembler/Mips/micromips32r6.txt +++ b/test/MC/Disassembler/Mips/micromips32r6.txt @@ -8,6 +8,10 @@ 0x78 0x80 0x00 0x19 # CHECK: addiupc $4, 100 +0x78 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 + +0x78 0x7e 0xff 0xff # CHECK: auipc $3, -1 + # CHECK: balc 14572256 0xb4 0x37 0x96 0xb8 diff --git a/test/MC/Mips/micromips32r6/valid.s b/test/MC/Mips/micromips32r6/valid.s index 869c5807298..db335ce599d 100644 --- a/test/MC/Mips/micromips32r6/valid.s +++ b/test/MC/Mips/micromips32r6/valid.s @@ -5,6 +5,8 @@ addiu $3, $4, 1234 # CHECK: addiu $3, $4, 1234 # encoding: [0x30,0x64,0x04,0xd2] addu $3, $4, $5 # CHECK: addu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x50] addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0x78,0x80,0x00,0x19] + aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0x78,0x7f,0x00,0x38] + auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0x78,0x7e,0xff,0xff] balc 14572256 # CHECK: balc 14572256 # encoding: [0xb4,0x37,0x96,0xb8] bc 14572256 # CHECK: bc 14572256 # encoding: [0x94,0x37,0x96,0xb8] bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x00,0x44,0x0b,0x3c]