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[PowerPC] Fix failure with STBRX when store is narrower than the bswap

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Fixes a crash caused by r296811 by truncating the input of the STBRX node
when the bswap is wider than i32.

Fixes https://bugs.llvm.org/show_bug.cgi?id=32140

Differential Revision: https://reviews.llvm.org/D30615


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297001 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nemanja Ivanovic 2017-03-06 07:32:13 +00:00
parent 8c95619c81
commit 521df0adae
2 changed files with 64 additions and 2 deletions
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7
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -11395,9 +11395,12 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
// it need to be shifted to the right side before STBRX.
EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
if (Op1VT.bitsGT(mVT)) {
int shift = Op1VT.getSizeInBits() - mVT.getSizeInBits();
int Shift = Op1VT.getSizeInBits() - mVT.getSizeInBits();
BSwapOp = DAG.getNode(ISD::SRL, dl, Op1VT, BSwapOp,
DAG.getConstant(shift, dl, MVT::i32));
DAG.getConstant(Shift, dl, MVT::i32));
// Need to truncate if this is a bswap of i64 stored as i32/i16.
if (Op1VT == MVT::i64)
BSwapOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BSwapOp);
}
SDValue Ops[] = {

59
test/CodeGen/PowerPC/pr32140.ll Normal file
View File

@ -0,0 +1,59 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -mtriple=powerpc64-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
@as = common local_unnamed_addr global i16 0, align 2
@bs = common local_unnamed_addr global i16 0, align 2
@ai = common local_unnamed_addr global i32 0, align 4
@bi = common local_unnamed_addr global i32 0, align 4
define void @bswapStorei64Toi32() {
; CHECK-LABEL: bswapStorei64Toi32:
; CHECK: # BB#0: # %entry
; CHECK: lwa 3, 0(3)
; CHECK-NEXT: rldicl 3, 3, 32, 32
; CHECK-NEXT: stwbrx 3, 0, 4
; CHECK-NEXT: blr
entry:
%0 = load i32, i32* @ai, align 4
%conv.i = sext i32 %0 to i64
%or26.i = tail call i64 @llvm.bswap.i64(i64 %conv.i)
%conv = trunc i64 %or26.i to i32
store i32 %conv, i32* @bi, align 4
ret void
}
define void @bswapStorei32Toi16() {
; CHECK-LABEL: bswapStorei32Toi16:
; CHECK: # BB#0: # %entry
; CHECK: lha 3, 0(3)
; CHECK-NEXT: srwi 3, 3, 16
; CHECK-NEXT: sthbrx 3, 0, 4
; CHECK-NEXT: blr
entry:
%0 = load i16, i16* @as, align 2
%conv.i = sext i16 %0 to i32
%or26.i = tail call i32 @llvm.bswap.i32(i32 %conv.i)
%conv = trunc i32 %or26.i to i16
store i16 %conv, i16* @bs, align 2
ret void
}
define void @bswapStorei64Toi16() {
; CHECK-LABEL: bswapStorei64Toi16:
; CHECK: # BB#0: # %entry
; CHECK: lha 3, 0(3)
; CHECK-NEXT: rldicl 3, 3, 16, 48
; CHECK-NEXT: sthbrx 3, 0, 4
; CHECK-NEXT: blr
entry:
%0 = load i16, i16* @as, align 2
%conv.i = sext i16 %0 to i64
%or26.i = tail call i64 @llvm.bswap.i64(i64 %conv.i)
%conv = trunc i64 %or26.i to i16
store i16 %conv, i16* @bs, align 2
ret void
}
declare i32 @llvm.bswap.i32(i32)
declare i64 @llvm.bswap.i64(i64)