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[mips] MIPSR6 Compact jump support
This patch adds support for compact jumps similiar to the previous compact branch support for MIPSR6. Unlike compact branches, compact jumps do not have a forbidden slot. As MipsInstrInfo::getEquivalentCompactForm can determine the correct expansion for jumps and branches for both microMIPS and MIPSR6, remove the unnecessary distinction in the delay slot filler. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265390 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Dardis
parent
515b87030b
commit
521f98ca01
@ -412,10 +412,11 @@ class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
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dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
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string AsmString = !strconcat(opstr, "\t$rt, $offset");
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list<dag> Pattern = [];
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bit isTerminator = 1;
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bit hasDelaySlot = 0;
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InstrItinClass Itinerary = itin;
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bit isCTI = 1;
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bit isBranch = 1;
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bit isIndirectBranch = 1;
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}
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class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
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@ -427,6 +428,7 @@ class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
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class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
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GPR32Opnd, II_JIALC> {
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bit isBarrier = 1;
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bit isTerminator = 1;
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list<Register> Defs = [AT];
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}
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@ -76,6 +76,18 @@ class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd, II_SCD>;
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class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
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class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
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class JIALC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
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GPR64Opnd> {
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bit isCall = 1;
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list<Register> Defs = [RA];
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}
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class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR64Opnd> {
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bit isBarrier = 1;
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bit isTerminator = 1;
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list<Register> Defs = [AT];
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}
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//===----------------------------------------------------------------------===//
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//
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// Instruction Definitions
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@ -107,7 +119,10 @@ let DecoderNamespace = "Mips32r6_64r6_GP64" in {
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def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
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def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
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}
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let isCodeGenOnly = 1 in {
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def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6;
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def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6;
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}
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//===----------------------------------------------------------------------===//
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//
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// Instruction Aliases
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@ -205,9 +205,6 @@ namespace {
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Iter replaceWithCompactBranch(MachineBasicBlock &MBB,
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Iter Branch, DebugLoc DL);
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Iter replaceWithCompactJump(MachineBasicBlock &MBB,
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Iter Jump, DebugLoc DL);
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/// This function checks if it is valid to move Candidate to the delay slot
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/// and returns true if it isn't. It also updates memory and register
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/// dependence information.
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@ -522,24 +519,6 @@ Iter Filler::replaceWithCompactBranch(MachineBasicBlock &MBB,
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return Branch;
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}
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// Replace Jumps with the compact jump instruction.
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Iter Filler::replaceWithCompactJump(MachineBasicBlock &MBB,
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Iter Jump, DebugLoc DL) {
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const MipsInstrInfo *TII =
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MBB.getParent()->getSubtarget<MipsSubtarget>().getInstrInfo();
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const MCInstrDesc &NewDesc = TII->get(Mips::JRC16_MM);
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MachineInstrBuilder MIB = BuildMI(MBB, Jump, DL, NewDesc);
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MIB.addReg(Jump->getOperand(0).getReg());
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Iter tmpIter = Jump;
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Jump = std::prev(Jump);
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MBB.erase(tmpIter);
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return Jump;
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}
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// For given opcode returns opcode of corresponding instruction with short
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// delay slot.
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static int getEquivalentCallShort(int Opcode) {
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@ -604,31 +583,21 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
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// corresponding instruction with short delay slot.
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DSI->setDesc(TII->get(getEquivalentCallShort(DSI->getOpcode())));
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}
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continue;
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}
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}
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// If instruction is BEQ or BNE with one ZERO register, then instead of
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// adding NOP replace this instruction with the corresponding compact
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// branch instruction, i.e. BEQZC or BNEZC.
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if (InMicroMipsMode) {
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if (TII->getEquivalentCompactForm(I)) {
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I = replaceWithCompactBranch(MBB, I, I->getDebugLoc());
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continue;
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}
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if (I->isIndirectBranch() || I->isReturn()) {
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// For microMIPS the PseudoReturn and PseudoIndirectBranch are always
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// expanded to JR_MM, so they can be replaced with JRC16_MM.
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I = replaceWithCompactJump(MBB, I, I->getDebugLoc());
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continue;
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}
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}
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// For microMIPS if instruction is BEQ or BNE with one ZERO register, then
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// instead of adding NOP replace this instruction with the corresponding
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// compact branch instruction, i.e. BEQZC or BNEZC. Additionally
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// PseudoReturn and PseudoIndirectBranch are expanded to JR_MM, so they can
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// be replaced with JRC16_MM.
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// For MIPSR6 attempt to produce the corresponding compact (no delay slot)
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// form of the branch. This should save putting in a NOP.
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if ((STI.hasMips32r6()) && TII->getEquivalentCompactForm(I)) {
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// form of the CTI. For indirect jumps this will not require inserting a
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// NOP and for branches will hopefully avoid requiring a NOP.
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if ((InMicroMipsMode || STI.hasMips32r6()) &&
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TII->getEquivalentCompactForm(I)) {
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I = replaceWithCompactBranch(MBB, I, I->getDebugLoc());
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continue;
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}
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@ -261,24 +261,40 @@ MipsInstrInfo::BranchType MipsInstrInfo::AnalyzeBranch(
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unsigned MipsInstrInfo::getEquivalentCompactForm(
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const MachineBasicBlock::iterator I) const {
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unsigned Opcode = I->getOpcode();
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bool canUseShortMMBranches =
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Subtarget.inMicroMipsMode() &&
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(Opcode == Mips::BNE || Opcode == Mips::BEQ) &&
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I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg();
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bool canUseShortMicroMipsCTI = false;
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if (Subtarget.hasMips32r6() || canUseShortMMBranches) {
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if (Subtarget.inMicroMipsMode()) {
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switch (Opcode) {
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case Mips::BNE:
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case Mips::BEQ:
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// microMIPS has NE,EQ branches that do not have delay slots provided one
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// of the operands is zero.
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if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
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canUseShortMicroMipsCTI = true;
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break;
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// For microMIPS the PseudoReturn and PseudoIndirectBranch are always
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// expanded to JR_MM, so they can be replaced with JRC16_MM.
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case Mips::JR:
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case Mips::PseudoReturn:
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case Mips::PseudoIndirectBranch:
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canUseShortMicroMipsCTI = true;
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break;
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}
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}
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if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
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switch (Opcode) {
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case Mips::B:
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return Mips::BC;
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case Mips::BAL:
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return Mips::BALC;
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case Mips::BEQ:
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if (canUseShortMMBranches)
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if (canUseShortMicroMipsCTI)
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return Mips::BEQZC_MM;
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else
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return Mips::BEQC;
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case Mips::BNE:
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if (canUseShortMMBranches)
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if (canUseShortMicroMipsCTI)
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return Mips::BNEZC_MM;
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else
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return Mips::BNEC;
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@ -298,7 +314,23 @@ unsigned MipsInstrInfo::getEquivalentCompactForm(
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return Mips::BLTUC;
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case Mips::BLTZ:
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return Mips::BLTZC;
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default:
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// For MIPSR6, the instruction 'jic' can be used for these cases. Some
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// tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
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case Mips::JR:
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case Mips::PseudoReturn:
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case Mips::PseudoIndirectBranch:
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if (canUseShortMicroMipsCTI)
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return Mips::JRC16_MM;
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return Mips::JIC;
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case Mips::JALRPseudo:
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return Mips::JIALC;
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case Mips::JR64:
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case Mips::PseudoReturn64:
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case Mips::PseudoIndirectBranch64:
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return Mips::JIC64;
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case Mips::JALR64Pseudo:
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return Mips::JIALC64;
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default:
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return 0;
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}
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}
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@ -343,19 +375,20 @@ MachineInstrBuilder
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MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
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MachineBasicBlock::iterator I) const {
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MachineInstrBuilder MIB;
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bool BranchWithZeroOperand = false;
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// Certain branches have two forms: e.g beq $1, $zero, dst vs beqz $1, dest
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// Pick the zero form of the branch for readable assembly and for greater
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// branch distance in non-microMIPS mode.
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if (I->isBranch() && I->getOperand(1).isReg() &&
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// FIXME: Certain atomic sequences on mips64 generate 32bit references to
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// Mips::ZERO, which is incorrect. This test should be updated to use
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// Subtarget.getABI().GetZeroReg() when those atomic sequences and others
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// are fixed.
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(I->getOperand(1).getReg() == Mips::ZERO ||
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I->getOperand(1).getReg() == Mips::ZERO_64)) {
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BranchWithZeroOperand = true;
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// FIXME: Certain atomic sequences on mips64 generate 32bit references to
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// Mips::ZERO, which is incorrect. This test should be updated to use
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// Subtarget.getABI().GetZeroReg() when those atomic sequences and others
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// are fixed.
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bool BranchWithZeroOperand =
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(I->isBranch() && !I->isPseudo() && I->getOperand(1).isReg() &&
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(I->getOperand(1).getReg() == Mips::ZERO ||
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I->getOperand(1).getReg() == Mips::ZERO_64));
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if (BranchWithZeroOperand) {
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switch (NewOpc) {
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case Mips::BEQC:
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NewOpc = Mips::BEQZC;
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@ -369,20 +402,43 @@ MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
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case Mips::BLTC:
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NewOpc = Mips::BLTZC;
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break;
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case Mips::BNEZC_MM:
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case Mips::BEQZC_MM:
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break;
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default:
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BranchWithZeroOperand = false;
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break;
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}
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}
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MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
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for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J)
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if (!(BranchWithZeroOperand && (J == 1)))
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// For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
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// immediate 0 as an operand and requires the removal of it's %RA<imp-def>
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// implicit operand as copying the implicit operations of the instructio we're
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// looking at will give us the correct flags.
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if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
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NewOpc == Mips::JIALC64) {
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if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
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MIB->RemoveOperand(0);
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for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
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MIB.addOperand(I->getOperand(J));
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}
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MIB.addImm(0);
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} else if (BranchWithZeroOperand) {
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// For MIPSR6 and microMIPS branches with an explicit zero operand, copy
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// everything after the zero.
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MIB.addOperand(I->getOperand(0));
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for (unsigned J = 2, E = I->getDesc().getNumOperands(); J < E; ++J) {
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MIB.addOperand(I->getOperand(J));
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}
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} else {
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// All other cases copy all other operands.
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for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
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MIB.addOperand(I->getOperand(J));
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}
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}
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MIB.copyImplicitOps(*I);
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MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end());
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return MIB;
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@ -1,21 +1,26 @@
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; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=static < %s | FileCheck %s
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; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=static -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=STATIC32
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; RUN: llc -march=mipsel -mcpu=mips64r6 -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=PIC
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; Function Attrs: nounwind
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define void @l() {
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entry:
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; PIC: jialc $25, 0
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%call = tail call i32 @k()
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; PIC: jialc $25, 0
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%call1 = tail call i32 @j()
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%cmp = icmp eq i32 %call, %call1
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; CHECK: bnec
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry:
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; CHECK: nop
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; CHECK: jal
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; STATIC: nop
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; STATIC: jal
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; PIC: jialc $25, 0
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tail call void @f(i32 signext -2)
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br label %if.end
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if.end: ; preds = %if.then, %entry
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; CHECK: jic $ra, 0
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ret void
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}
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@ -28,19 +33,23 @@ declare void @f(i32 signext)
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; Function Attrs: define void @l2() {
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define void @l2() {
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entry:
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; PIC: jialc $25, 0
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%call = tail call i32 @k()
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; PIC: jialc $25, 0
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%call1 = tail call i32 @i()
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%cmp = icmp eq i32 %call, %call1
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; CHECK beqc
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br i1 %cmp, label %if.end, label %if.then
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if.then: ; preds = %entry:
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; CHECK: nop
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; CHECK: jal
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; STATIC: nop
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; STATIC: jal
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; PIC: jialc $25, 0
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tail call void @f(i32 signext -1)
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br label %if.end
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if.end: ; preds = %entry, %if.then
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; CHECK: jic $ra, 0
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ret void
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}
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@ -49,18 +58,21 @@ declare i32 @i()
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; Function Attrs: nounwind
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define void @l3() {
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entry:
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; PIC: jialc $25, 0
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%call = tail call i32 @k()
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%cmp = icmp slt i32 %call, 0
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; CHECK : bgez
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry:
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; CHECK: nop
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; CHECK: jal
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; STATIC: nop
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; STATIC: jal
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; PIC: jialc $25, 0
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tail call void @f(i32 signext 0)
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br label %if.end
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if.end: ; preds = %if.then, %entry
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; CHECK: jic $ra, 0
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ret void
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}
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@ -73,83 +85,122 @@ entry:
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry:
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; CHECK: nop
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; CHECK: jal
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; STATIC: nop
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; STATIC: jal
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tail call void @f(i32 signext 1)
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br label %if.end
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if.end: ; preds = %if.then, %entry
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; CHECK: jic $ra, 0
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ret void
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}
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; Function Attrs: nounwind
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define void @l5() {
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entry:
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; PIC: jialc $25, 0
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%call = tail call i32 @k()
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; PIC: jialc $25, 0
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%cmp = icmp sgt i32 %call, 0
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; CHECK: blezc
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry:
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; CHECK: nop
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; CHECK: jal
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; STATIC: nop
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; STATIC: jal
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; PIC: jialc $25, 0
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tail call void @f(i32 signext 2)
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br label %if.end
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if.end: ; preds = %if.then, %entry
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; CHECK: jic $ra, 0
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ret void
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}
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; Function Attrs: nounwind
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define void @l6() {
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entry:
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; PIC: jialc $25, 0
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%call = tail call i32 @k()
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; PIC: jialc $25, 0
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%cmp = icmp sgt i32 %call, -1
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; CHECK: bltzc
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry:
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; CHECK: nop
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; CHECK: jal
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; STATIC: nop
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; STATIC: jal
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; PIC: jialc $25, 0
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tail call void @f(i32 signext 3)
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br label %if.end
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||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
; CHECK: jic $ra, 0
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @l7() {
|
||||
entry:
|
||||
; PIC: jialc $25, 0
|
||||
%call = tail call i32 @k()
|
||||
%cmp = icmp eq i32 %call, 0
|
||||
; CHECK: bnezc
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry:
|
||||
; CHECK: nop
|
||||
; CHECK: jal
|
||||
; STATIC: nop
|
||||
; STATIC: jal
|
||||
; PIC: jialc $25, 0
|
||||
tail call void @f(i32 signext 4)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
; CHECK: jic $ra, 0
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @l8() {
|
||||
entry:
|
||||
; PIC: jialc $25, 0
|
||||
%call = tail call i32 @k()
|
||||
%cmp = icmp eq i32 %call, 0
|
||||
; CHECK: beqzc
|
||||
br i1 %cmp, label %if.end, label %if.then
|
||||
|
||||
if.then: ; preds = %entry:
|
||||
; CHECK: nop
|
||||
; CHECK: jal
|
||||
; STATIC: nop
|
||||
; STATIC: jal
|
||||
; PIC: jialc $25, 0
|
||||
tail call void @f(i32 signext 5)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %entry, %if.then
|
||||
; CHECK: jic $ra, 0
|
||||
ret void
|
||||
}
|
||||
|
||||
define i32 @l9(i8* ()* %i) #0 {
|
||||
entry:
|
||||
%i.addr = alloca i8* ()*, align 4
|
||||
store i8* ()* %i, i8* ()** %i.addr, align 4
|
||||
; STATIC32: jal
|
||||
; STATIC32: nop
|
||||
; PIC: jialc $25, 0
|
||||
%call = call i32 @k()
|
||||
; PIC: jialc $25, 0
|
||||
%cmp = icmp ne i32 %call, 0
|
||||
; CHECK: beqzc
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry
|
||||
%0 = load i8* ()*, i8* ()** %i.addr, align 4
|
||||
; CHECK: jialc $25, 0
|
||||
%call1 = call i8* %0()
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
; CHECK: jic $ra, 0
|
||||
ret i32 -1
|
||||
}
|
||||
|
||||
@ -1,18 +1,18 @@
|
||||
; Test the 'call' instruction and the tailcall variant.
|
||||
|
||||
; FIXME: We should remove the need for -enable-mips-tail-calls
|
||||
; RUN: llc -march=mips -mcpu=mips32 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
|
||||
; RUN: llc -march=mips -mcpu=mips32r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
|
||||
; RUN: llc -march=mips -mcpu=mips32r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
|
||||
; RUN: llc -march=mips -mcpu=mips32r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+fp64,+nooddspreg -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
|
||||
; RUN: llc -march=mips64 -mcpu=mips4 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
|
||||
; RUN: llc -march=mips64 -mcpu=mips64 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
|
||||
; RUN: llc -march=mips -mcpu=mips32 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
|
||||
; RUN: llc -march=mips -mcpu=mips32r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
|
||||
; RUN: llc -march=mips -mcpu=mips32r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
|
||||
; RUN: llc -march=mips -mcpu=mips32r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+fp64,+nooddspreg -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C
|
||||
; RUN: llc -march=mips64 -mcpu=mips4 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
|
||||
; RUN: llc -march=mips64 -mcpu=mips64 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r6 -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=R6C
|
||||
|
||||
declare void @extern_void_void()
|
||||
declare i32 @extern_i32_void()
|
||||
@ -25,7 +25,8 @@ define i32 @call_void_void() {
|
||||
|
||||
; N64: ld $[[TGT:[0-9]+]], %call16(extern_void_void)($gp)
|
||||
|
||||
; ALL: jalr $[[TGT]]
|
||||
; NOT-R6C: jalr $[[TGT]]
|
||||
; R6C: jialc $[[TGT]], 0
|
||||
|
||||
call void @extern_void_void()
|
||||
ret i32 0
|
||||
@ -38,7 +39,8 @@ define i32 @call_i32_void() {
|
||||
|
||||
; N64: ld $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp)
|
||||
|
||||
; ALL: jalr $[[TGT]]
|
||||
; NOT-R6C: jalr $[[TGT]]
|
||||
; R6C: jialc $[[TGT]], 0
|
||||
|
||||
%1 = call i32 @extern_i32_void()
|
||||
%2 = add i32 %1, 1
|
||||
@ -55,9 +57,9 @@ define float @call_float_void() {
|
||||
|
||||
; N64: ld $[[TGT:[0-9]+]], %call16(extern_float_void)($gp)
|
||||
|
||||
; ALL: jalr $[[TGT]]
|
||||
; NOT-R6C: jalr $[[TGT]]
|
||||
; R6C: jialc $[[TGT]], 0
|
||||
|
||||
; O32: move $gp, $[[GP]]
|
||||
|
||||
%1 = call float @extern_float_void()
|
||||
%2 = fadd float %1, 1.0
|
||||
@ -71,8 +73,7 @@ define void @musttail_call_void_void() {
|
||||
|
||||
; N64: ld $[[TGT:[0-9]+]], %call16(extern_void_void)($gp)
|
||||
|
||||
; NOT-R6: jr $[[TGT]]
|
||||
; R6: r6.jr $[[TGT]]
|
||||
; ALL: jr $[[TGT]]
|
||||
|
||||
musttail call void @extern_void_void()
|
||||
ret void
|
||||
@ -85,8 +86,7 @@ define i32 @musttail_call_i32_void() {
|
||||
|
||||
; N64: ld $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp)
|
||||
|
||||
; NOT-R6: jr $[[TGT]]
|
||||
; R6: r6.jr $[[TGT]]
|
||||
; ALL: jr $[[TGT]]
|
||||
|
||||
%1 = musttail call i32 @extern_i32_void()
|
||||
ret i32 %1
|
||||
@ -99,8 +99,7 @@ define float @musttail_call_float_void() {
|
||||
|
||||
; N64: ld $[[TGT:[0-9]+]], %call16(extern_float_void)($gp)
|
||||
|
||||
; NOT-R6: jr $[[TGT]]
|
||||
; R6: r6.jr $[[TGT]]
|
||||
; ALL: jr $[[TGT]]
|
||||
|
||||
%1 = musttail call float @extern_float_void()
|
||||
ret float %1
|
||||
@ -110,7 +109,9 @@ define i32 @indirect_call_void_void(void ()* %addr) {
|
||||
; ALL-LABEL: indirect_call_void_void:
|
||||
|
||||
; ALL: move $25, $4
|
||||
; ALL: jalr $25
|
||||
; NOT-R6C: jalr $25
|
||||
; R6C: jialc $25, 0
|
||||
|
||||
|
||||
call void %addr()
|
||||
ret i32 0
|
||||
@ -120,7 +121,9 @@ define i32 @indirect_call_i32_void(i32 ()* %addr) {
|
||||
; ALL-LABEL: indirect_call_i32_void:
|
||||
|
||||
; ALL: move $25, $4
|
||||
; ALL: jalr $25
|
||||
; NOT-R6C: jalr $25
|
||||
; R6C: jialc $25, 0
|
||||
|
||||
|
||||
%1 = call i32 %addr()
|
||||
%2 = add i32 %1, 1
|
||||
@ -131,7 +134,9 @@ define float @indirect_call_float_void(float ()* %addr) {
|
||||
; ALL-LABEL: indirect_call_float_void:
|
||||
|
||||
; ALL: move $25, $4
|
||||
; ALL: jalr $25
|
||||
; NOT-R6C: jalr $25
|
||||
; R6C: jialc $25, 0
|
||||
|
||||
|
||||
%1 = call float %addr()
|
||||
%2 = fadd float %1, 1.0
|
||||
@ -178,7 +183,8 @@ define hidden void @thunk_undef_double(i32 %this, double %volume) unnamed_addr a
|
||||
; ALL-LABEL: thunk_undef_double:
|
||||
; O32: # implicit-def: %A2
|
||||
; O32: # implicit-def: %A3
|
||||
; ALL: jr $25
|
||||
; ALL: jr $25
|
||||
|
||||
tail call void @undef_double(i32 undef, double undef) #8
|
||||
ret void
|
||||
}
|
||||
@ -190,7 +196,8 @@ define i32 @jal_only_allows_symbols() {
|
||||
; ALL-NOT: {{jal }}
|
||||
; ALL: addiu $[[TGT:[0-9]+]], $zero, 1234
|
||||
; ALL-NOT: {{jal }}
|
||||
; ALL: jalr $[[TGT]]
|
||||
; NOT-R6C: jalr $[[TGT]]
|
||||
; R6C: jialc $[[TGT]], 0
|
||||
; ALL-NOT: {{jal }}
|
||||
|
||||
call void () inttoptr (i32 1234 to void ()*)()
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
|
||||
; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
|
||||
; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6C
|
||||
; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
|
||||
; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
|
||||
@ -15,16 +15,19 @@
|
||||
define i32 @br(i8 *%addr) {
|
||||
; ALL-LABEL: br:
|
||||
; NOT-R6: jr $4 # <MCInst #{{[0-9]+}} JR
|
||||
; R6: jr $4 # <MCInst #{{[0-9]+}} JALR
|
||||
; R6C: jic $4, 0 # <MCInst #{{[0-9]+}} JIC
|
||||
|
||||
|
||||
; ALL: $BB0_1: # %L1
|
||||
; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
; ALL: addiu $2, $zero, 0
|
||||
|
||||
; ALL: $BB0_2: # %L2
|
||||
; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
; ALL: addiu $2, $zero, 1
|
||||
|
||||
entry:
|
||||
|
||||
@ -11,19 +11,27 @@
|
||||
; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
|
||||
; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
|
||||
; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=R6
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=R6C
|
||||
; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
|
||||
; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=R6
|
||||
|
||||
; FIXME: for the test ret_double_0x0, the delay slot of jr cannot be filled
|
||||
; as mthc1 has unmodeled side effects. This is an artifact of our backend.
|
||||
; Force the delay slot filler off to check that the sequence jr $ra; nop is
|
||||
; turned into jic 0, $ra.
|
||||
|
||||
; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 \
|
||||
; RUN: -check-prefix=R6C
|
||||
|
||||
define void @ret_void() {
|
||||
; ALL-LABEL: ret_void:
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
; R6C-DAG: jic $ra, 0 # <MCInst #{{[0-9]+}} JIC
|
||||
|
||||
ret void
|
||||
}
|
||||
@ -173,6 +181,7 @@ define float @ret_float_0x3() {
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
; R6C-DAG: jic $ra, 0 # <MCInst #{{[0-9]+}} JIC
|
||||
|
||||
; float constants are written as double constants
|
||||
ret float 0x36b8000000000000
|
||||
@ -191,6 +200,7 @@ define double @ret_double_0x0() {
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
; R6C-DAG: jic $ra, 0 # <MCInst #{{[0-9]+}} JIC
|
||||
|
||||
ret double 0x0000000000000000
|
||||
}
|
||||
@ -204,6 +214,7 @@ define double @ret_double_0x3() {
|
||||
|
||||
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
|
||||
; R6C-DAG: jic $ra, 0 # <MCInst #{{[0-9]+}} JIC
|
||||
|
||||
ret double 0x0000000000000003
|
||||
}
|
||||
|
||||
@ -1,11 +1,11 @@
|
||||
; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips4 -mattr=+soft-float -O1 \
|
||||
; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT
|
||||
; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT -check-prefix=PRER6
|
||||
; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64 -mattr=+soft-float -O1 \
|
||||
; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT
|
||||
; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT -check-prefix=PRER6
|
||||
; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r2 -mattr=+soft-float -O1 \
|
||||
; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT
|
||||
; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT -check-prefix=PRER6
|
||||
; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r6 -mattr=+soft-float -O1 \
|
||||
; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=CMP_CC_FMT
|
||||
; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=CMP_CC_FMT -check-prefix=R6
|
||||
|
||||
@gld0 = external global fp128
|
||||
@gld1 = external global fp128
|
||||
@ -544,10 +544,11 @@ entry:
|
||||
}
|
||||
|
||||
; ALL-LABEL: load_LD_float:
|
||||
; ALL: ld $[[R0:[0-9]+]], %got_disp(gf1)
|
||||
; ALL: lw $4, 0($[[R0]])
|
||||
; ALL: ld $25, %call16(__extendsftf2)
|
||||
; ALL: jalr $25
|
||||
; ALL: ld $[[R0:[0-9]+]], %got_disp(gf1)
|
||||
; ALL: lw $4, 0($[[R0]])
|
||||
; ALL: ld $25, %call16(__extendsftf2)
|
||||
; PRER6: jalr $25
|
||||
; R6: jialc $25, 0
|
||||
|
||||
define fp128 @load_LD_float() {
|
||||
entry:
|
||||
@ -557,10 +558,11 @@ entry:
|
||||
}
|
||||
|
||||
; ALL-LABEL: load_LD_double:
|
||||
; ALL: ld $[[R0:[0-9]+]], %got_disp(gd1)
|
||||
; ALL: ld $4, 0($[[R0]])
|
||||
; ALL: ld $25, %call16(__extenddftf2)
|
||||
; ALL: jalr $25
|
||||
; ALL: ld $[[R0:[0-9]+]], %got_disp(gd1)
|
||||
; ALL: ld $4, 0($[[R0]])
|
||||
; ALL: ld $25, %call16(__extenddftf2)
|
||||
; PRER6: jalr $25
|
||||
; R6: jialc $25, 0
|
||||
|
||||
define fp128 @load_LD_double() {
|
||||
entry:
|
||||
@ -585,13 +587,14 @@ entry:
|
||||
}
|
||||
|
||||
; ALL-LABEL: store_LD_float:
|
||||
; ALL: ld $[[R0:[0-9]+]], %got_disp(gld1)
|
||||
; ALL: ld $4, 0($[[R0]])
|
||||
; ALL: ld $5, 8($[[R0]])
|
||||
; ALL: ld $25, %call16(__trunctfsf2)
|
||||
; ALL: jalr $25
|
||||
; ALL: ld $[[R1:[0-9]+]], %got_disp(gf1)
|
||||
; ALL: sw $2, 0($[[R1]])
|
||||
; ALL: ld $[[R0:[0-9]+]], %got_disp(gld1)
|
||||
; ALL: ld $4, 0($[[R0]])
|
||||
; ALL: ld $5, 8($[[R0]])
|
||||
; ALL: ld $25, %call16(__trunctfsf2)
|
||||
; PRER6: jalr $25
|
||||
; R6: jialc $25, 0
|
||||
; ALL: ld $[[R1:[0-9]+]], %got_disp(gf1)
|
||||
; ALL: sw $2, 0($[[R1]])
|
||||
|
||||
define void @store_LD_float() {
|
||||
entry:
|
||||
@ -602,13 +605,14 @@ entry:
|
||||
}
|
||||
|
||||
; ALL-LABEL: store_LD_double:
|
||||
; ALL: ld $[[R0:[0-9]+]], %got_disp(gld1)
|
||||
; ALL: ld $4, 0($[[R0]])
|
||||
; ALL: ld $5, 8($[[R0]])
|
||||
; ALL: ld $25, %call16(__trunctfdf2)
|
||||
; ALL: jalr $25
|
||||
; ALL: ld $[[R1:[0-9]+]], %got_disp(gd1)
|
||||
; ALL: sd $2, 0($[[R1]])
|
||||
; ALL: ld $[[R0:[0-9]+]], %got_disp(gld1)
|
||||
; ALL: ld $4, 0($[[R0]])
|
||||
; ALL: ld $5, 8($[[R0]])
|
||||
; ALL: ld $25, %call16(__trunctfdf2)
|
||||
; PRER6: jalr $25
|
||||
; R6: jialc $25, 0
|
||||
; ALL: ld $[[R1:[0-9]+]], %got_disp(gd1)
|
||||
; ALL: sd $2, 0($[[R1]])
|
||||
|
||||
define void @store_LD_double() {
|
||||
entry:
|
||||
@ -648,7 +652,8 @@ entry:
|
||||
; ALL: move $[[R2:[0-9]+]], $9
|
||||
; ALL: move $[[R3:[0-9]+]], $8
|
||||
; ALL: ld $25, %call16(__gttf2)($gp)
|
||||
; ALL: jalr $25
|
||||
; PRER6: jalr $25
|
||||
; R6: jialc $25, 0
|
||||
|
||||
; C_CC_FMT: slti $[[CC:[0-9]+]], $2, 1
|
||||
; C_CC_FMT: movz $[[R1]], $[[R3]], $[[CC]]
|
||||
|
||||
@ -165,6 +165,8 @@ a:
|
||||
jr $25 # CHECK: jr $25 # encoding: [0x03,0x20,0x00,0x09]
|
||||
jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09]
|
||||
jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
|
||||
jialc $15, 16161 # CHECK: jialc $15, 16161 # encoding: [0xf8,0x0f,0x3f,0x21]
|
||||
jic $12, -3920 # CHECK: jic $12, -3920 # encoding: [0xd8,0x0c,0xf0,0xb0]
|
||||
ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43]
|
||||
lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0x49,0x52,0x34,0xb7]
|
||||
sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user