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[X86][SSE] Added vector udiv combine tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281842 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim
parent
063b3271dc
commit
52c60cece6
199
test/CodeGen/X86/combine-udiv.ll
Normal file
199
test/CodeGen/X86/combine-udiv.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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; fold (udiv undef, x) -> 0
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define <4 x i32> @combine_vec_udiv_undef0(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_udiv_undef0:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_udiv_undef0:
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; AVX: # BB#0:
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; AVX-NEXT: retq
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%1 = udiv <4 x i32> undef, %x
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ret <4 x i32> %1
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}
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; fold (udiv x, undef) -> undef
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define <4 x i32> @combine_vec_udiv_undef1(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_udiv_undef1:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_udiv_undef1:
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; AVX: # BB#0:
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; AVX-NEXT: retq
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%1 = udiv <4 x i32> %x, undef
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ret <4 x i32> %1
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}
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; fold (udiv x, (1 << c)) -> x >>u c
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define <4 x i32> @combine_vec_udiv_by_pow2a(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_udiv_by_pow2a:
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; SSE: # BB#0:
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; SSE-NEXT: psrld $2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_udiv_by_pow2a:
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; AVX: # BB#0:
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; AVX-NEXT: vpsrld $2, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = udiv <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
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ret <4 x i32> %1
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}
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define <4 x i32> @combine_vec_udiv_by_pow2b(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_udiv_by_pow2b:
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; SSE: # BB#0:
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; SSE-NEXT: pextrd $1, %xmm0, %eax
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; SSE-NEXT: shrl $2, %eax
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; SSE-NEXT: pextrd $2, %xmm0, %ecx
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; SSE-NEXT: pextrd $3, %xmm0, %edx
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; SSE-NEXT: pinsrd $1, %eax, %xmm0
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; SSE-NEXT: shrl $3, %ecx
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; SSE-NEXT: pinsrd $2, %ecx, %xmm0
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; SSE-NEXT: shrl $4, %edx
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; SSE-NEXT: pinsrd $3, %edx, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_udiv_by_pow2b:
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; AVX: # BB#0:
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; AVX-NEXT: vpextrd $1, %xmm0, %eax
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; AVX-NEXT: shrl $2, %eax
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; AVX-NEXT: vpinsrd $1, %eax, %xmm0, %xmm1
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; AVX-NEXT: vpextrd $2, %xmm0, %eax
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; AVX-NEXT: shrl $3, %eax
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; AVX-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1
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; AVX-NEXT: vpextrd $3, %xmm0, %eax
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; AVX-NEXT: shrl $4, %eax
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; AVX-NEXT: vpinsrd $3, %eax, %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = udiv <4 x i32> %x, <i32 1, i32 4, i32 8, i32 16>
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ret <4 x i32> %1
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}
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; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
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define <4 x i32> @combine_vec_udiv_by_shl_pow2a(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_udiv_by_shl_pow2a:
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; SSE: # BB#0:
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; SSE-NEXT: pslld $23, %xmm1
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; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
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; SSE-NEXT: cvttps2dq %xmm1, %xmm2
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; SSE-NEXT: pslld $2, %xmm2
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; SSE-NEXT: pextrd $1, %xmm0, %eax
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; SSE-NEXT: pextrd $1, %xmm2, %ecx
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %ecx
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; SSE-NEXT: movl %eax, %ecx
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; SSE-NEXT: movd %xmm0, %eax
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; SSE-NEXT: movd %xmm2, %esi
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %esi
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; SSE-NEXT: movd %eax, %xmm1
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; SSE-NEXT: pinsrd $1, %ecx, %xmm1
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; SSE-NEXT: pextrd $2, %xmm0, %eax
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; SSE-NEXT: pextrd $2, %xmm2, %ecx
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %ecx
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; SSE-NEXT: pinsrd $2, %eax, %xmm1
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; SSE-NEXT: pextrd $3, %xmm0, %eax
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; SSE-NEXT: pextrd $3, %xmm2, %ecx
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %ecx
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; SSE-NEXT: pinsrd $3, %eax, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_udiv_by_shl_pow2a:
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; AVX: # BB#0:
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; AVX-NEXT: vpbroadcastd {{.*}}(%rip), %xmm2
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; AVX-NEXT: vpsllvd %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vpextrd $1, %xmm1, %ecx
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; AVX-NEXT: vpextrd $1, %xmm0, %eax
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; AVX-NEXT: xorl %edx, %edx
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; AVX-NEXT: divl %ecx
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; AVX-NEXT: movl %eax, %ecx
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; AVX-NEXT: vmovd %xmm1, %esi
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; AVX-NEXT: vmovd %xmm0, %eax
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; AVX-NEXT: xorl %edx, %edx
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; AVX-NEXT: divl %esi
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; AVX-NEXT: vmovd %eax, %xmm2
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; AVX-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
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; AVX-NEXT: vpextrd $2, %xmm1, %ecx
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; AVX-NEXT: vpextrd $2, %xmm0, %eax
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; AVX-NEXT: xorl %edx, %edx
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; AVX-NEXT: divl %ecx
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; AVX-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2
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; AVX-NEXT: vpextrd $3, %xmm1, %ecx
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; AVX-NEXT: vpextrd $3, %xmm0, %eax
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; AVX-NEXT: xorl %edx, %edx
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; AVX-NEXT: divl %ecx
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; AVX-NEXT: vpinsrd $3, %eax, %xmm2, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> <i32 4, i32 4, i32 4, i32 4>, %y
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%2 = udiv <4 x i32> %x, %1
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ret <4 x i32> %2
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}
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define <4 x i32> @combine_vec_udiv_by_shl_pow2b(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_udiv_by_shl_pow2b:
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; SSE: # BB#0:
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; SSE-NEXT: pslld $23, %xmm1
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; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
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; SSE-NEXT: cvttps2dq %xmm1, %xmm2
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm2
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; SSE-NEXT: pextrd $1, %xmm0, %eax
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; SSE-NEXT: pextrd $1, %xmm2, %ecx
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %ecx
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; SSE-NEXT: movl %eax, %ecx
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; SSE-NEXT: movd %xmm0, %eax
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; SSE-NEXT: movd %xmm2, %esi
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %esi
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; SSE-NEXT: movd %eax, %xmm1
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; SSE-NEXT: pinsrd $1, %ecx, %xmm1
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; SSE-NEXT: pextrd $2, %xmm0, %eax
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; SSE-NEXT: pextrd $2, %xmm2, %ecx
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %ecx
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; SSE-NEXT: pinsrd $2, %eax, %xmm1
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; SSE-NEXT: pextrd $3, %xmm0, %eax
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; SSE-NEXT: pextrd $3, %xmm2, %ecx
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %ecx
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; SSE-NEXT: pinsrd $3, %eax, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_udiv_by_shl_pow2b:
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; AVX: # BB#0:
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; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [1,4,8,16]
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; AVX-NEXT: vpsllvd %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vpextrd $1, %xmm1, %ecx
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; AVX-NEXT: vpextrd $1, %xmm0, %eax
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; AVX-NEXT: xorl %edx, %edx
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; AVX-NEXT: divl %ecx
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; AVX-NEXT: movl %eax, %ecx
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; AVX-NEXT: vmovd %xmm1, %esi
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; AVX-NEXT: vmovd %xmm0, %eax
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; AVX-NEXT: xorl %edx, %edx
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; AVX-NEXT: divl %esi
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; AVX-NEXT: vmovd %eax, %xmm2
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; AVX-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
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; AVX-NEXT: vpextrd $2, %xmm1, %ecx
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; AVX-NEXT: vpextrd $2, %xmm0, %eax
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; AVX-NEXT: xorl %edx, %edx
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; AVX-NEXT: divl %ecx
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; AVX-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2
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; AVX-NEXT: vpextrd $3, %xmm1, %ecx
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; AVX-NEXT: vpextrd $3, %xmm0, %eax
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; AVX-NEXT: xorl %edx, %edx
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; AVX-NEXT: divl %ecx
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; AVX-NEXT: vpinsrd $3, %eax, %xmm2, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> <i32 1, i32 4, i32 8, i32 16>, %y
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%2 = udiv <4 x i32> %x, %1
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ret <4 x i32> %2
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}
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