Add named timer groups for the different stages of register allocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121604 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-12-11 00:19:56 +00:00
parent 4680dec5fb
commit 533f58ecdd
3 changed files with 23 additions and 9 deletions

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@ -153,6 +153,9 @@ protected:
void verify(); void verify();
#endif #endif
// Use this group name for NamedRegionTimer.
static const char *TimerGroupName;
private: private:
void seedLiveVirtRegs(std::priority_queue<std::pair<float, unsigned> >&); void seedLiveVirtRegs(std::priority_queue<std::pair<float, unsigned> >&);

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@ -42,6 +42,7 @@
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "llvm/Support/Timer.h"
#include <cstdlib> #include <cstdlib>
@ -56,6 +57,8 @@ static cl::opt<bool>
VerifyRegAlloc("verify-regalloc", VerifyRegAlloc("verify-regalloc",
cl::desc("Verify live intervals before renaming")); cl::desc("Verify live intervals before renaming"));
const char *RegAllocBase::TimerGroupName = "Register Allocation";
namespace { namespace {
class PhysicalRegisterDescription : public AbstractRegisterDescription { class PhysicalRegisterDescription : public AbstractRegisterDescription {
@ -204,6 +207,7 @@ void RegAllocBase::LiveUnionArray::init(LiveIntervalUnion::Allocator &allocator,
} }
void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) { void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled);
TRI = &vrm.getTargetRegInfo(); TRI = &vrm.getTargetRegInfo();
MRI = &vrm.getRegInfo(); MRI = &vrm.getRegInfo();
VRM = &vrm; VRM = &vrm;
@ -364,6 +368,7 @@ RegAllocBase::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
// Add newly allocated physical registers to the MBB live in sets. // Add newly allocated physical registers to the MBB live in sets.
void RegAllocBase::addMBBLiveIns(MachineFunction *MF) { void RegAllocBase::addMBBLiveIns(MachineFunction *MF) {
NamedRegionTimer T("MBB Live Ins", TimerGroupName, TimePassesIsEnabled);
typedef SmallVector<MachineBasicBlock*, 8> MBBVec; typedef SmallVector<MachineBasicBlock*, 8> MBBVec;
MBBVec liveInMBBs; MBBVec liveInMBBs;
MachineBasicBlock &entryMBB = *MF->begin(); MachineBasicBlock &entryMBB = *MF->begin();

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@ -35,6 +35,7 @@
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "llvm/Support/Timer.h"
using namespace llvm; using namespace llvm;
@ -58,7 +59,7 @@ public:
/// Return the pass name. /// Return the pass name.
virtual const char* getPassName() const { virtual const char* getPassName() const {
return "Basic Register Allocator"; return "Greedy Register Allocator";
} }
/// RAGreedy analysis usage. /// RAGreedy analysis usage.
@ -254,17 +255,19 @@ unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
// Try to reassign interfering physical register. Priority among // Try to reassign interfering physical register. Priority among
// PhysRegSpillCands does not matter yet, because the reassigned virtual // PhysRegSpillCands does not matter yet, because the reassigned virtual
// registers will still be assigned to physical registers. // registers will still be assigned to physical registers.
for (SmallVectorImpl<unsigned>::iterator PhysRegI = ReassignCands.begin(), {
PhysRegE = ReassignCands.end(); PhysRegI != PhysRegE; ++PhysRegI) { NamedRegionTimer T("Reassign", TimerGroupName, TimePassesIsEnabled);
if (reassignInterferences(VirtReg, *PhysRegI)) for (SmallVectorImpl<unsigned>::iterator PhysRegI = ReassignCands.begin(),
// Reassignment successfull. The caller may allocate now to this PhysReg. PhysRegE = ReassignCands.end(); PhysRegI != PhysRegE; ++PhysRegI)
return *PhysRegI; if (reassignInterferences(VirtReg, *PhysRegI))
// Reassignment successfull. Allocate now to this PhysReg.
return *PhysRegI;
} }
PhysRegSpillCands.insert(PhysRegSpillCands.end(), ReassignCands.begin(), PhysRegSpillCands.insert(PhysRegSpillCands.end(), ReassignCands.begin(),
ReassignCands.end()); ReassignCands.end());
// Try to spill another interfering reg with less spill weight. // Try to spill another interfering reg with less spill weight.
NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
// //
// FIXME: do this in two steps: (1) check for unspillable interferences while // FIXME: do this in two steps: (1) check for unspillable interferences while
// accumulating spill weight; (2) spill the interferences with lowest // accumulating spill weight; (2) spill the interferences with lowest
@ -305,8 +308,11 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
addMBBLiveIns(MF); addMBBLiveIns(MF);
// Run rewriter // Run rewriter
std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter()); {
rewriter->runOnMachineFunction(*MF, *VRM, LIS); NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled);
std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
rewriter->runOnMachineFunction(*MF, *VRM, LIS);
}
// The pass output is in VirtRegMap. Release all the transient data. // The pass output is in VirtRegMap. Release all the transient data.
releaseMemory(); releaseMemory();