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Add named timer groups for the different stages of register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121604 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -153,6 +153,9 @@ protected:
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void verify();
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void verify();
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#endif
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#endif
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// Use this group name for NamedRegionTimer.
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static const char *TimerGroupName;
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private:
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private:
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void seedLiveVirtRegs(std::priority_queue<std::pair<float, unsigned> >&);
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void seedLiveVirtRegs(std::priority_queue<std::pair<float, unsigned> >&);
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@ -42,6 +42,7 @@
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/Timer.h"
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#include <cstdlib>
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#include <cstdlib>
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@ -56,6 +57,8 @@ static cl::opt<bool>
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VerifyRegAlloc("verify-regalloc",
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VerifyRegAlloc("verify-regalloc",
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cl::desc("Verify live intervals before renaming"));
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cl::desc("Verify live intervals before renaming"));
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const char *RegAllocBase::TimerGroupName = "Register Allocation";
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namespace {
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namespace {
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class PhysicalRegisterDescription : public AbstractRegisterDescription {
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class PhysicalRegisterDescription : public AbstractRegisterDescription {
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@ -204,6 +207,7 @@ void RegAllocBase::LiveUnionArray::init(LiveIntervalUnion::Allocator &allocator,
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}
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}
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void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
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void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
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NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled);
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TRI = &vrm.getTargetRegInfo();
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TRI = &vrm.getTargetRegInfo();
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MRI = &vrm.getRegInfo();
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MRI = &vrm.getRegInfo();
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VRM = &vrm;
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VRM = &vrm;
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@ -364,6 +368,7 @@ RegAllocBase::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
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// Add newly allocated physical registers to the MBB live in sets.
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// Add newly allocated physical registers to the MBB live in sets.
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void RegAllocBase::addMBBLiveIns(MachineFunction *MF) {
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void RegAllocBase::addMBBLiveIns(MachineFunction *MF) {
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NamedRegionTimer T("MBB Live Ins", TimerGroupName, TimePassesIsEnabled);
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typedef SmallVector<MachineBasicBlock*, 8> MBBVec;
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typedef SmallVector<MachineBasicBlock*, 8> MBBVec;
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MBBVec liveInMBBs;
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MBBVec liveInMBBs;
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MachineBasicBlock &entryMBB = *MF->begin();
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MachineBasicBlock &entryMBB = *MF->begin();
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@ -35,6 +35,7 @@
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/Timer.h"
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using namespace llvm;
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using namespace llvm;
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@ -58,7 +59,7 @@ public:
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/// Return the pass name.
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/// Return the pass name.
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virtual const char* getPassName() const {
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virtual const char* getPassName() const {
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return "Basic Register Allocator";
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return "Greedy Register Allocator";
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}
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}
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/// RAGreedy analysis usage.
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/// RAGreedy analysis usage.
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@ -254,17 +255,19 @@ unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
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// Try to reassign interfering physical register. Priority among
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// Try to reassign interfering physical register. Priority among
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// PhysRegSpillCands does not matter yet, because the reassigned virtual
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// PhysRegSpillCands does not matter yet, because the reassigned virtual
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// registers will still be assigned to physical registers.
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// registers will still be assigned to physical registers.
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for (SmallVectorImpl<unsigned>::iterator PhysRegI = ReassignCands.begin(),
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{
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PhysRegE = ReassignCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
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NamedRegionTimer T("Reassign", TimerGroupName, TimePassesIsEnabled);
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if (reassignInterferences(VirtReg, *PhysRegI))
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for (SmallVectorImpl<unsigned>::iterator PhysRegI = ReassignCands.begin(),
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// Reassignment successfull. The caller may allocate now to this PhysReg.
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PhysRegE = ReassignCands.end(); PhysRegI != PhysRegE; ++PhysRegI)
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return *PhysRegI;
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if (reassignInterferences(VirtReg, *PhysRegI))
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// Reassignment successfull. Allocate now to this PhysReg.
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return *PhysRegI;
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}
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}
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PhysRegSpillCands.insert(PhysRegSpillCands.end(), ReassignCands.begin(),
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PhysRegSpillCands.insert(PhysRegSpillCands.end(), ReassignCands.begin(),
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ReassignCands.end());
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ReassignCands.end());
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// Try to spill another interfering reg with less spill weight.
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// Try to spill another interfering reg with less spill weight.
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NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
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//
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//
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// FIXME: do this in two steps: (1) check for unspillable interferences while
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// FIXME: do this in two steps: (1) check for unspillable interferences while
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// accumulating spill weight; (2) spill the interferences with lowest
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// accumulating spill weight; (2) spill the interferences with lowest
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@ -305,8 +308,11 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
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addMBBLiveIns(MF);
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addMBBLiveIns(MF);
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// Run rewriter
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// Run rewriter
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std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
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{
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rewriter->runOnMachineFunction(*MF, *VRM, LIS);
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NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled);
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std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
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rewriter->runOnMachineFunction(*MF, *VRM, LIS);
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}
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// The pass output is in VirtRegMap. Release all the transient data.
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// The pass output is in VirtRegMap. Release all the transient data.
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releaseMemory();
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releaseMemory();
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