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[ARM] Move SMULW[B|T] isel to DAG Combine
Create nodes for smulwb and smulwt and move their selection from DAGToDAG to DAG combine. smlawb and smlawt can then be selected using tablegen. Added some helper functions to detect shift patterns as well as a wrapper around SimplifyDemandBits. Added a couple of extra tests. Differential Revision: https://reviews.llvm.org/D30708 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297716 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sam Parker
parent
6095a7948d
commit
53c73db7b9
@ -2379,6 +2379,10 @@ public:
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unsigned Depth = 0,
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bool AssumeSingleUse = false) const;
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/// Helper wrapper around SimplifyDemandedBits
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bool SimplifyDemandedBits(SDValue Op, APInt &DemandedMask,
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DAGCombinerInfo &DCI) const;
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/// Determine which of the bits specified in Mask are known to be either zero
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/// or one and return them in the KnownZero/KnownOne bitsets.
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virtual void computeKnownBitsForTargetNode(const SDValue Op,
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@ -471,6 +471,21 @@ TargetLowering::TargetLoweringOpt::SimplifyDemandedBits(SDNode *User,
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return true;
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}
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bool TargetLowering::SimplifyDemandedBits(SDValue Op, APInt &DemandedMask,
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DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
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!DCI.isBeforeLegalizeOps());
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APInt KnownZero, KnownOne;
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bool Simplified = SimplifyDemandedBits(Op, DemandedMask, KnownZero, KnownOne,
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TLO);
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if (Simplified)
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DCI.CommitTargetLoweringOpt(TLO);
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return Simplified;
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}
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/// Look at Op. At this point, we know that only the DemandedMask bits of the
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/// result of Op are ever used downstream. If we can use this information to
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/// simplify Op, create a new simplified DAG node and return true, returning the
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@ -247,8 +247,6 @@ private:
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void SelectConcatVector(SDNode *N);
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void SelectCMPZ(SDNode *N, bool &SwitchEQNEToPLMI);
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bool trySMLAWSMULW(SDNode *N);
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void SelectCMP_SWAP(SDNode *N);
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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@ -2559,141 +2557,6 @@ bool ARMDAGToDAGISel::tryABSOp(SDNode *N){
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return false;
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}
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static bool SearchSignedMulShort(SDValue SignExt, unsigned *Opc, SDValue &Src1,
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bool Accumulate) {
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// For SM*WB, we need to some form of sext.
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// For SM*WT, we need to search for (sra X, 16)
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// Src1 then gets set to X.
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if ((SignExt.getOpcode() == ISD::SIGN_EXTEND ||
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SignExt.getOpcode() == ISD::SIGN_EXTEND_INREG ||
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SignExt.getOpcode() == ISD::AssertSext) &&
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SignExt.getValueType() == MVT::i32) {
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*Opc = Accumulate ? ARM::SMLAWB : ARM::SMULWB;
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Src1 = SignExt.getOperand(0);
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return true;
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}
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if (SignExt.getOpcode() != ISD::SRA)
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return false;
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ConstantSDNode *SRASrc1 = dyn_cast<ConstantSDNode>(SignExt.getOperand(1));
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if (!SRASrc1 || SRASrc1->getZExtValue() != 16)
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return false;
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SDValue Op0 = SignExt.getOperand(0);
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// The sign extend operand for SM*WB could be generated by a shl and ashr.
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if (Op0.getOpcode() == ISD::SHL) {
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SDValue SHL = Op0;
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ConstantSDNode *SHLSrc1 = dyn_cast<ConstantSDNode>(SHL.getOperand(1));
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if (!SHLSrc1 || SHLSrc1->getZExtValue() != 16)
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return false;
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*Opc = Accumulate ? ARM::SMLAWB : ARM::SMULWB;
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Src1 = Op0.getOperand(0);
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return true;
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}
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*Opc = Accumulate ? ARM::SMLAWT : ARM::SMULWT;
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Src1 = SignExt.getOperand(0);
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return true;
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}
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static bool SearchSignedMulLong(SDValue OR, unsigned *Opc, SDValue &Src0,
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SDValue &Src1, bool Accumulate) {
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// First we look for:
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// (add (or (srl ?, 16), (shl ?, 16)))
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if (OR.getOpcode() != ISD::OR)
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return false;
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SDValue SRL = OR.getOperand(0);
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SDValue SHL = OR.getOperand(1);
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if (SRL.getOpcode() != ISD::SRL || SHL.getOpcode() != ISD::SHL) {
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SRL = OR.getOperand(1);
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SHL = OR.getOperand(0);
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if (SRL.getOpcode() != ISD::SRL || SHL.getOpcode() != ISD::SHL)
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return false;
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}
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ConstantSDNode *SRLSrc1 = dyn_cast<ConstantSDNode>(SRL.getOperand(1));
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ConstantSDNode *SHLSrc1 = dyn_cast<ConstantSDNode>(SHL.getOperand(1));
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if (!SRLSrc1 || !SHLSrc1 || SRLSrc1->getZExtValue() != 16 ||
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SHLSrc1->getZExtValue() != 16)
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return false;
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// The first operands to the shifts need to be the two results from the
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// same smul_lohi node.
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if ((SRL.getOperand(0).getNode() != SHL.getOperand(0).getNode()) ||
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SRL.getOperand(0).getOpcode() != ISD::SMUL_LOHI)
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return false;
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SDNode *SMULLOHI = SRL.getOperand(0).getNode();
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if (SRL.getOperand(0) != SDValue(SMULLOHI, 0) ||
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SHL.getOperand(0) != SDValue(SMULLOHI, 1))
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return false;
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// Now we have:
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// (add (or (srl (smul_lohi ?, ?), 16), (shl (smul_lohi ?, ?), 16)))
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// For SMLAW[B|T] smul_lohi will take a 32-bit and a 16-bit arguments.
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// For SMLAWB the 16-bit value will signed extended somehow.
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// For SMLAWT only the SRA is required.
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// Check both sides of SMUL_LOHI
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if (SearchSignedMulShort(SMULLOHI->getOperand(0), Opc, Src1, Accumulate)) {
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Src0 = SMULLOHI->getOperand(1);
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} else if (SearchSignedMulShort(SMULLOHI->getOperand(1), Opc, Src1,
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Accumulate)) {
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Src0 = SMULLOHI->getOperand(0);
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} else {
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return false;
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}
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return true;
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}
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bool ARMDAGToDAGISel::trySMLAWSMULW(SDNode *N) {
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if (!Subtarget->hasV6Ops() ||
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(Subtarget->isThumb() && !Subtarget->hasThumb2()))
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return false;
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SDLoc dl(N);
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SDValue Src0 = N->getOperand(0);
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SDValue Src1 = N->getOperand(1);
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SDValue A, B;
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unsigned Opc = 0;
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if (N->getOpcode() == ISD::ADD) {
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if (Src0.getOpcode() != ISD::OR && Src1.getOpcode() != ISD::OR)
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return false;
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SDValue Acc;
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if (SearchSignedMulLong(Src0, &Opc, A, B, true)) {
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Acc = Src1;
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} else if (SearchSignedMulLong(Src1, &Opc, A, B, true)) {
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Acc = Src0;
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} else {
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return false;
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}
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if (Opc == 0)
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return false;
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SDValue Ops[] = { A, B, Acc, getAL(CurDAG, dl),
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CurDAG->getRegister(0, MVT::i32) };
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CurDAG->SelectNodeTo(N, Opc, MVT::i32, MVT::Other, Ops);
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return true;
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} else if (N->getOpcode() == ISD::OR &&
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SearchSignedMulLong(SDValue(N, 0), &Opc, A, B, false)) {
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if (Opc == 0)
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return false;
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SDValue Ops[] = { A, B, getAL(CurDAG, dl),
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CurDAG->getRegister(0, MVT::i32)};
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CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
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return true;
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}
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return false;
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}
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/// We've got special pseudo-instructions for these
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void ARMDAGToDAGISel::SelectCMP_SWAP(SDNode *N) {
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unsigned Opcode;
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@ -2822,11 +2685,6 @@ void ARMDAGToDAGISel::Select(SDNode *N) {
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switch (N->getOpcode()) {
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default: break;
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case ISD::ADD:
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case ISD::OR:
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if (trySMLAWSMULW(N))
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return;
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break;
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case ISD::WRITE_REGISTER:
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if (tryWriteRegister(N))
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return;
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@ -1337,6 +1337,8 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case ARMISD::UMAAL: return "ARMISD::UMAAL";
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case ARMISD::UMLAL: return "ARMISD::UMLAL";
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case ARMISD::SMLAL: return "ARMISD::SMLAL";
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case ARMISD::SMULWB: return "ARMISD::SMULWB";
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case ARMISD::SMULWT: return "ARMISD::SMULWT";
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case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
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case ARMISD::BFI: return "ARMISD::BFI";
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case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
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@ -1446,6 +1448,40 @@ Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
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// Lowering Code
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//===----------------------------------------------------------------------===//
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static bool isSRL16(const SDValue &Op) {
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if (Op.getOpcode() != ISD::SRL)
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return false;
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if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
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return Const->getZExtValue() == 16;
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return false;
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}
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static bool isSRA16(const SDValue &Op) {
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if (Op.getOpcode() != ISD::SRA)
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return false;
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if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
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return Const->getZExtValue() == 16;
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return false;
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}
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static bool isSHL16(const SDValue &Op) {
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if (Op.getOpcode() != ISD::SHL)
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return false;
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if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
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return Const->getZExtValue() == 16;
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return false;
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}
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// Check for a signed 16-bit value. We special case SRA because it makes it
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// more simple when also looking for SRAs that aren't sign extending a
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// smaller value. Without the check, we'd need to take extra care with
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// checking order for some operations.
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static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
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if (isSRA16(Op))
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return isSHL16(Op.getOperand(0));
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return DAG.ComputeNumSignBits(Op) == 17;
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}
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/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
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static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
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switch (CC) {
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@ -9945,6 +9981,67 @@ static SDValue PerformANDCombine(SDNode *N,
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return SDValue();
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}
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// Try combining OR nodes to SMULWB, SMULWT.
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static SDValue PerformORCombineToSMULWBT(SDNode *OR,
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TargetLowering::DAGCombinerInfo &DCI,
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const ARMSubtarget *Subtarget) {
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if (!Subtarget->hasV6Ops() ||
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(Subtarget->isThumb() &&
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(!Subtarget->hasThumb2() || !Subtarget->hasDSP())))
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return SDValue();
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SDValue SRL = OR->getOperand(0);
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SDValue SHL = OR->getOperand(1);
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if (SRL.getOpcode() != ISD::SRL || SHL.getOpcode() != ISD::SHL) {
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SRL = OR->getOperand(1);
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SHL = OR->getOperand(0);
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}
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if (!isSRL16(SRL) || !isSHL16(SHL))
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return SDValue();
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// The first operands to the shifts need to be the two results from the
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// same smul_lohi node.
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if ((SRL.getOperand(0).getNode() != SHL.getOperand(0).getNode()) ||
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SRL.getOperand(0).getOpcode() != ISD::SMUL_LOHI)
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return SDValue();
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SDNode *SMULLOHI = SRL.getOperand(0).getNode();
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if (SRL.getOperand(0) != SDValue(SMULLOHI, 0) ||
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SHL.getOperand(0) != SDValue(SMULLOHI, 1))
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return SDValue();
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// Now we have:
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// (or (srl (smul_lohi ?, ?), 16), (shl (smul_lohi ?, ?), 16)))
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// For SMUL[B|T] smul_lohi will take a 32-bit and a 16-bit arguments.
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// For SMUWB the 16-bit value will signed extended somehow.
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// For SMULWT only the SRA is required.
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// Check both sides of SMUL_LOHI
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SDValue OpS16 = SMULLOHI->getOperand(0);
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SDValue OpS32 = SMULLOHI->getOperand(1);
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SelectionDAG &DAG = DCI.DAG;
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if (!isS16(OpS16, DAG) && !isSRA16(OpS16)) {
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OpS16 = OpS32;
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OpS32 = SMULLOHI->getOperand(0);
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}
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SDLoc dl(OR);
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unsigned Opcode = 0;
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if (isS16(OpS16, DAG))
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Opcode = ARMISD::SMULWB;
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else if (isSRA16(OpS16)) {
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Opcode = ARMISD::SMULWT;
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OpS16 = OpS16->getOperand(0);
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}
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else
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return SDValue();
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SDValue Res = DAG.getNode(Opcode, dl, MVT::i32, OpS32, OpS16);
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DAG.ReplaceAllUsesOfValueWith(SDValue(OR, 0), Res);
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return SDValue(OR, 0);
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}
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/// PerformORCombine - Target-specific dag combine xforms for ISD::OR
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static SDValue PerformORCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI,
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@ -9982,6 +10079,8 @@ static SDValue PerformORCombine(SDNode *N,
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// fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
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if (SDValue Result = combineSelectAndUseCommutative(N, false, DCI))
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return Result;
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if (SDValue Result = PerformORCombineToSMULWBT(N, DCI, Subtarget))
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return Result;
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}
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// The code below optimizes (or (and X, Y), Z).
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@ -11781,6 +11880,20 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
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return PerformVLDCombine(N, DCI);
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case ARMISD::BUILD_VECTOR:
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return PerformARMBUILD_VECTORCombine(N, DCI);
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case ARMISD::SMULWB: {
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unsigned BitWidth = N->getValueType(0).getSizeInBits();
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APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 16);
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if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))
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return SDValue();
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break;
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}
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case ARMISD::SMULWT: {
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unsigned BitWidth = N->getValueType(0).getSizeInBits();
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APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 16);
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if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))
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return SDValue();
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break;
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}
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case ISD::INTRINSIC_VOID:
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case ISD::INTRINSIC_W_CHAIN:
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switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
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@ -175,6 +175,8 @@ class InstrItineraryData;
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VMULLs, // ...signed
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VMULLu, // ...unsigned
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SMULWB, // Signed multiply word by half word, bottom
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SMULWT, // Signed multiply word by half word, top
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UMLAL, // 64bit Unsigned Accumulate Multiply
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SMLAL, // 64bit Signed Accumulate Multiply
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UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
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@ -183,6 +183,9 @@ def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY,
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[SDNPHasChain, SDNPInGlue, SDNPOutGlue,
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SDNPMayStore, SDNPMayLoad]>;
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def ARMsmulwb : SDNode<"ARMISD::SMULWB", SDTIntBinOp, []>;
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def ARMsmulwt : SDNode<"ARMISD::SMULWT", SDTIntBinOp, []>;
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//===----------------------------------------------------------------------===//
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// ARM Instruction Predicate Definitions.
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//
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@ -4100,13 +4103,13 @@ multiclass AI_smul<string opc> {
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def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
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IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
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[]>,
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[(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>,
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Requires<[IsARM, HasV5TE]>,
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Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
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def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
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IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
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[]>,
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[(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>,
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Requires<[IsARM, HasV5TE]>,
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Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
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}
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@ -4153,14 +4156,16 @@ multiclass AI_smla<string opc> {
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def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
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(ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
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IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
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[]>,
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[(set GPRnopc:$Rd,
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(add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))]>,
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Requires<[IsARM, HasV5TE, UseMulOps]>,
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Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
|
||||
|
||||
def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
|
||||
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
|
||||
IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
|
||||
[]>,
|
||||
[(set GPRnopc:$Rd,
|
||||
(add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))]>,
|
||||
Requires<[IsARM, HasV5TE, UseMulOps]>,
|
||||
Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
|
||||
}
|
||||
|
||||
@ -2676,8 +2676,10 @@ def t2SMULTB : T2ThreeRegSMUL<0b001, 0b10, "smultb",
|
||||
def t2SMULTT : T2ThreeRegSMUL<0b001, 0b11, "smultt",
|
||||
[(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)),
|
||||
(sra rGPR:$Rm, (i32 16))))]>;
|
||||
def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb", []>;
|
||||
def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt", []>;
|
||||
def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb",
|
||||
[(set rGPR:$Rd, (ARMsmulwb rGPR:$Rn, rGPR:$Rm))]>;
|
||||
def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt",
|
||||
[(set rGPR:$Rd, (ARMsmulwt rGPR:$Rn, rGPR:$Rm))]>;
|
||||
|
||||
def : Thumb2DSPPat<(mul sext_16_node:$Rm, sext_16_node:$Rn),
|
||||
(t2SMULBB rGPR:$Rm, rGPR:$Rn)>;
|
||||
@ -2712,8 +2714,10 @@ def t2SMLATB : T2FourRegSMLA<0b001, 0b10, "smlatb",
|
||||
def t2SMLATT : T2FourRegSMLA<0b001, 0b11, "smlatt",
|
||||
[(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)),
|
||||
(sra rGPR:$Rm, (i32 16)))))]>;
|
||||
def t2SMLAWB : T2FourRegSMLA<0b011, 0b00, "smlawb", []>;
|
||||
def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt", []>;
|
||||
def t2SMLAWB : T2FourRegSMLA<0b011, 0b00, "smlawb",
|
||||
[(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwb rGPR:$Rn, rGPR:$Rm)))]>;
|
||||
def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt",
|
||||
[(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwt rGPR:$Rn, rGPR:$Rm)))]>;
|
||||
|
||||
def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, sext_16_node:$Rm)),
|
||||
(t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
|
||||
|
||||
@ -262,3 +262,32 @@ define i32 @f21(i32 %a, i32 %x, i16 %y) {
|
||||
%tmp5 = add i32 %a, %tmp4
|
||||
ret i32 %tmp5
|
||||
}
|
||||
|
||||
@global_b = external global i16, align 2
|
||||
|
||||
define i32 @f22(i32 %a) {
|
||||
; CHECK-LABEL: f22:
|
||||
; CHECK: smulwb r0, r0, r1
|
||||
; CHECK-THUMBV6-NOT: smulwb
|
||||
%b = load i16, i16* @global_b, align 2
|
||||
%sext = sext i16 %b to i64
|
||||
%conv = sext i32 %a to i64
|
||||
%mul = mul nsw i64 %sext, %conv
|
||||
%shr37 = lshr i64 %mul, 16
|
||||
%conv4 = trunc i64 %shr37 to i32
|
||||
ret i32 %conv4
|
||||
}
|
||||
|
||||
define i32 @f23(i32 %a, i32 %c) {
|
||||
; CHECK-LABEL: f23:
|
||||
; CHECK: smlawb r0, r0, r2, r1
|
||||
; CHECK-THUMBV6-NOT: smlawb
|
||||
%b = load i16, i16* @global_b, align 2
|
||||
%sext = sext i16 %b to i64
|
||||
%conv = sext i32 %a to i64
|
||||
%mul = mul nsw i64 %sext, %conv
|
||||
%shr49 = lshr i64 %mul, 16
|
||||
%conv5 = trunc i64 %shr49 to i32
|
||||
%add = add nsw i32 %conv5, %c
|
||||
ret i32 %add
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user