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Implement LowerReturn_64 for SPARC v9.
Integer return values are sign or zero extended by the callee, and
structs up to 32 bytes in size can be returned in registers.
The CC_Sparc64 CallingConv definition is shared between
LowerFormalArguments_64 and LowerReturn_64. Function arguments and
return values are passed in the same registers.
The inreg flag is also used for return values. This is required to handle
C functions returning structs containing floats and ints:
struct ifp {
int i;
float f;
};
struct ifp f(void);
LLVM IR:
define inreg { i32, float } @f() {
...
ret { i32, float } %retval
}
The ABI requires that %retval.i is returned in the high bits of %i0
while %retval.f goes in %f1.
Without the inreg return value attribute, %retval.i would go in %i0 and
%retval.f would go in %f3 which is a more efficient way of returning
%multiple values, but it is not ABI compliant for returning C structs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178966 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
2b9355f2d9
commit
53d4bcf35e
@ -150,22 +150,32 @@ static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT,
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SDValue
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SparcTargetLowering::LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc dl, SelectionDAG &DAG) const {
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DebugLoc DL, SelectionDAG &DAG) const {
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if (Subtarget->is64Bit())
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return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
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return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
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}
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SDValue
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SparcTargetLowering::LowerReturn_32(SDValue Chain,
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CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc DL, SelectionDAG &DAG) const {
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MachineFunction &MF = DAG.getMachineFunction();
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// CCValAssign - represent the assignment of the return value to locations.
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SmallVector<CCValAssign, 16> RVLocs;
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// CCState - Info about the registers and stack slot.
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CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
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CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
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DAG.getTarget(), RVLocs, *DAG.getContext());
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// Analize return values.
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CCInfo.AnalyzeReturn(Outs, Subtarget->is64Bit() ? CC_Sparc64 : RetCC_Sparc32);
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// Analyze return values.
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CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
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SDValue Flag;
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SmallVector<SDValue, 4> RetOps(1, Chain);
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@ -177,7 +187,7 @@ SparcTargetLowering::LowerReturn(SDValue Chain,
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CCValAssign &VA = RVLocs[i];
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assert(VA.isRegLoc() && "Can only return in registers!");
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Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
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Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(),
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OutVals[i], Flag);
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// Guarantee that all emitted copies are stuck together with flags.
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@ -192,8 +202,8 @@ SparcTargetLowering::LowerReturn(SDValue Chain,
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unsigned Reg = SFI->getSRetReturnReg();
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if (!Reg)
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llvm_unreachable("sret virtual register not created in the entry block");
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SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
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Chain = DAG.getCopyToReg(Chain, dl, SP::I0, Val, Flag);
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SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
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Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag);
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Flag = Chain.getValue(1);
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RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy()));
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RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
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@ -206,7 +216,85 @@ SparcTargetLowering::LowerReturn(SDValue Chain,
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if (Flag.getNode())
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RetOps.push_back(Flag);
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return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other,
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return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other,
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&RetOps[0], RetOps.size());
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}
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// Lower return values for the 64-bit ABI.
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// Return values are passed the exactly the same way as function arguments.
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SDValue
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SparcTargetLowering::LowerReturn_64(SDValue Chain,
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CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc DL, SelectionDAG &DAG) const {
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// CCValAssign - represent the assignment of the return value to locations.
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SmallVector<CCValAssign, 16> RVLocs;
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// CCState - Info about the registers and stack slot.
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CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
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DAG.getTarget(), RVLocs, *DAG.getContext());
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// Analyze return values.
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CCInfo.AnalyzeReturn(Outs, CC_Sparc64);
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SDValue Flag;
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SmallVector<SDValue, 4> RetOps(1, Chain);
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// The second operand on the return instruction is the return address offset.
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// The return address is always %i7+8 with the 64-bit ABI.
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RetOps.push_back(DAG.getConstant(8, MVT::i32));
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// Copy the result values into the output registers.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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CCValAssign &VA = RVLocs[i];
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assert(VA.isRegLoc() && "Can only return in registers!");
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SDValue OutVal = OutVals[i];
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// Integer return values must be sign or zero extended by the callee.
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switch (VA.getLocInfo()) {
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case CCValAssign::SExt:
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OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
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break;
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case CCValAssign::ZExt:
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OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
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break;
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case CCValAssign::AExt:
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OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
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default:
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break;
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}
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// The custom bit on an i32 return value indicates that it should be passed
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// in the high bits of the register.
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if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
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OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
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DAG.getConstant(32, MVT::i32));
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// The next value may go in the low bits of the same register.
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// Handle both at once.
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if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
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SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
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OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
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// Skip the next value, it's already done.
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++i;
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}
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}
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Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
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// Guarantee that all emitted copies are stuck together with flags.
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Flag = Chain.getValue(1);
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RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
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}
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RetOps[0] = Chain; // Update chain.
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// Add the flag if we have it.
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if (Flag.getNode())
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RetOps.push_back(Flag);
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return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other,
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&RetOps[0], RetOps.size());
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}
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@ -102,6 +102,16 @@ namespace llvm {
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc dl, SelectionDAG &DAG) const;
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SDValue LowerReturn_32(SDValue Chain,
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CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc DL, SelectionDAG &DAG) const;
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SDValue LowerReturn_64(SDValue Chain,
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CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc DL, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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@ -40,6 +40,9 @@ let Predicates = [Is64Bit] in {
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def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>;
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def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>;
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def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>;
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def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>;
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defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, I64Regs>;
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defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, I64Regs>;
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defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, I64Regs>;
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@ -203,16 +206,22 @@ def LDXri : F3_2<3, 0b001011,
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// Extending loads to i64.
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def : Pat<(i64 (zextloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
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def : Pat<(i64 (zextloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
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def : Pat<(i64 (extloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
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def : Pat<(i64 (extloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
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def : Pat<(i64 (sextloadi8 ADDRrr:$addr)), (LDSBrr ADDRrr:$addr)>;
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def : Pat<(i64 (sextloadi8 ADDRri:$addr)), (LDSBri ADDRri:$addr)>;
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def : Pat<(i64 (zextloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>;
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def : Pat<(i64 (zextloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>;
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def : Pat<(i64 (extloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>;
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def : Pat<(i64 (extloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>;
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def : Pat<(i64 (sextloadi16 ADDRrr:$addr)), (LDSHrr ADDRrr:$addr)>;
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def : Pat<(i64 (sextloadi16 ADDRri:$addr)), (LDSHri ADDRri:$addr)>;
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def : Pat<(i64 (zextloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>;
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def : Pat<(i64 (zextloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;
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def : Pat<(i64 (extloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>;
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def : Pat<(i64 (extloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;
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// Sign-extending load of i32 into i64 is a new SPARC v9 instruction.
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def LDSWrr : F3_1<3, 0b001011,
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@ -132,3 +132,87 @@ define i32 @inreg_ii(i32 inreg %a0, ; high bits of %i0
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%rv = sub i32 %a1, %a0
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ret i32 %rv
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}
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; Structs up to 32 bytes in size can be returned in registers.
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; CHECK: ret_i64_pair
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; CHECK: ldx [%i2], %i0
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; CHECK: ldx [%i3], %i1
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define { i64, i64 } @ret_i64_pair(i32 %a0, i32 %a1, i64* %p, i64* %q) {
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%r1 = load i64* %p
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%rv1 = insertvalue { i64, i64 } undef, i64 %r1, 0
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store i64 0, i64* %p
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%r2 = load i64* %q
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%rv2 = insertvalue { i64, i64 } %rv1, i64 %r2, 1
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ret { i64, i64 } %rv2
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}
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; This is not a C struct, each member uses 8 bytes.
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; CHECK: ret_i32_float_pair
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; CHECK: ld [%i2], %i0
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; CHECK: ld [%i3], %f3
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define { i32, float } @ret_i32_float_pair(i32 %a0, i32 %a1,
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i32* %p, float* %q) {
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%r1 = load i32* %p
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%rv1 = insertvalue { i32, float } undef, i32 %r1, 0
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store i32 0, i32* %p
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%r2 = load float* %q
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%rv2 = insertvalue { i32, float } %rv1, float %r2, 1
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ret { i32, float } %rv2
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}
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; This is a C struct, each member uses 4 bytes.
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; CHECK: ret_i32_float_packed
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; CHECK: ld [%i2], [[R:%[gilo][0-7]]]
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; CHECK: sllx [[R]], 32, %i0
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; CHECK: ld [%i3], %f1
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define inreg { i32, float } @ret_i32_float_packed(i32 %a0, i32 %a1,
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i32* %p, float* %q) {
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%r1 = load i32* %p
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%rv1 = insertvalue { i32, float } undef, i32 %r1, 0
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store i32 0, i32* %p
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%r2 = load float* %q
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%rv2 = insertvalue { i32, float } %rv1, float %r2, 1
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ret { i32, float } %rv2
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}
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; The C frontend should use i64 to return { i32, i32 } structs, but verify that
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; we don't miscompile thi case where both struct elements are placed in %i0.
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; CHECK: ret_i32_packed
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; CHECK: ld [%i2], [[R1:%[gilo][0-7]]]
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; CHECK: ld [%i3], [[R2:%[gilo][0-7]]]
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; CHECK: sllx [[R2]], 32, [[R3:%[gilo][0-7]]]
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; CHECK: or [[R3]], [[R1]], %i0
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define inreg { i32, i32 } @ret_i32_packed(i32 %a0, i32 %a1,
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i32* %p, i32* %q) {
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%r1 = load i32* %p
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%rv1 = insertvalue { i32, i32 } undef, i32 %r1, 1
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store i32 0, i32* %p
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%r2 = load i32* %q
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%rv2 = insertvalue { i32, i32 } %rv1, i32 %r2, 0
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ret { i32, i32 } %rv2
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}
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; The return value must be sign-extended to 64 bits.
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; CHECK: ret_sext
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; CHECK: sra %i0, 0, %i0
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define signext i32 @ret_sext(i32 %a0) {
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ret i32 %a0
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}
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; CHECK: ret_zext
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; CHECK: srl %i0, 0, %i0
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define zeroext i32 @ret_zext(i32 %a0) {
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ret i32 %a0
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}
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; CHECK: ret_nosext
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; CHECK-NOT: sra
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define signext i32 @ret_nosext(i32 signext %a0) {
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ret i32 %a0
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}
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; CHECK: ret_nozext
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; CHECK-NOT: srl
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define signext i32 @ret_nozext(i32 signext %a0) {
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ret i32 %a0
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}
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