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[X86] Remove INVPCID and SMAP feature flags. They aren't currently used by any instructions and not tested.

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If we implement intrinsics for their instructions in the future, the feature flags can be added back with proper testing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294561 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2017-02-09 06:50:59 +00:00
parent 4b9bffa31e
commit 53daf1a1ce
3 changed files with 1 additions and 16 deletions
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2
lib/Support/Host.cpp
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@ -1368,11 +1368,9 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1); Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1);
Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
Features["smap"] = HasLeaf7 && ((EBX >> 20) & 1);
Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);

9
lib/Target/X86/X86.td
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@ -217,10 +217,6 @@ def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",
def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions", def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
"PadShortFunctions", "true", "PadShortFunctions", "true",
"Pad short functions">; "Pad short functions">;
def FeatureINVPCID : SubtargetFeature<"invpcid", "HasInvPCId", "true",
"Invalidate Process-Context Identifier">;
def FeatureSMAP : SubtargetFeature<"smap", "HasSMAP", "true",
"Supervisor Mode Access Protection">;
def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true", def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",
"Enable Software Guard Extensions">; "Enable Software Guard Extensions">;
def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true", def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
@ -496,7 +492,6 @@ def HSWFeatures : ProcessorFeatures<IVBFeatures.Value, [
FeatureFMA, FeatureFMA,
FeatureLZCNT, FeatureLZCNT,
FeatureMOVBE, FeatureMOVBE,
FeatureINVPCID,
FeatureRTM, FeatureRTM,
FeatureHLE, FeatureHLE,
FeatureSlowIncDec FeatureSlowIncDec
@ -509,8 +504,7 @@ def : HaswellProc<"core-avx2">; // Legacy alias.
def BDWFeatures : ProcessorFeatures<HSWFeatures.Value, [ def BDWFeatures : ProcessorFeatures<HSWFeatures.Value, [
FeatureADX, FeatureADX,
FeatureRDSEED, FeatureRDSEED
FeatureSMAP
]>; ]>;
class BroadwellProc<string Name> : ProcModel<Name, HaswellModel, class BroadwellProc<string Name> : ProcModel<Name, HaswellModel,
BDWFeatures.Value, []>; BDWFeatures.Value, []>;
@ -785,7 +779,6 @@ def: ProcessorModel<"znver1", BtVer2Model, [
FeatureRDRAND, FeatureRDRAND,
FeatureRDSEED, FeatureRDSEED,
FeatureSHA, FeatureSHA,
FeatureSMAP,
FeatureSSE4A, FeatureSSE4A,
FeatureSlowSHLD, FeatureSlowSHLD,
FeatureX87, FeatureX87,

6
lib/Target/X86/X86Subtarget.h
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@ -274,12 +274,6 @@ protected:
/// Processor supports MPX - Memory Protection Extensions /// Processor supports MPX - Memory Protection Extensions
bool HasMPX; bool HasMPX;
/// Processor supports Invalidate Process-Context Identifier
bool HasInvPCId;
/// Processor has Supervisor Mode Access Protection
bool HasSMAP;
/// Processor has Software Guard Extensions /// Processor has Software Guard Extensions
bool HasSGX; bool HasSGX;