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Use BuildMI more
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5299 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
1531b63421
commit
54e898e690
@ -70,11 +70,8 @@ CreateSETUWConst(const TargetMachine& target, uint32_t C,
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else
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{ // unsigned or small signed value that fits in simm13 field of OR
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assert(smallNegValue || (C & ~MAXSIMM) == 0);
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miOR = new MachineInstr(OR);
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miOR->SetMachineOperandReg(0, target.getRegInfo().getZeroRegNum());
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miOR->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,
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sC);
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miOR->SetMachineOperandVal(2,MachineOperand::MO_VirtualRegister,dest);
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miOR = BuildMI(OR, 3).addMReg(target.getRegInfo().getZeroRegNum())
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.addSImm(sC).addRegDef(dest);
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}
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mvec.push_back(miOR);
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}
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@ -180,7 +177,7 @@ CreateSETXLabel(const TargetMachine& target,
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MachineInstr* MI;
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MI = BuildMI(SETHI, 2).addReg(val).addRegDef(tmpReg);
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MI = BuildMI(SETHI, 2).addPCDisp(val).addRegDef(tmpReg);
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MI->setOperandHi64(0);
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mvec.push_back(MI);
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@ -501,11 +498,10 @@ UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
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CreateZeroExtensionInstructions(target, F, val, storeVal, 8*srcSize,
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mvec, mcfi);
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}
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MachineInstr* store=new MachineInstr(ChooseStoreInstruction(storeType));
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store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, storeVal);
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store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
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store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed,offset);
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mvec.push_back(store);
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unsigned FPReg = target.getRegInfo().getFramePointer();
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mvec.push_back(BuildMI(ChooseStoreInstruction(storeType), 3)
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.addReg(storeVal).addMReg(FPReg).addSImm(offset));
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// Load instruction loads [%fp+offset] to `dest'.
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// The type of the load opCode is the floating point type that matches the
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@ -513,11 +509,8 @@ UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
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// On SparcV9: float for int or smaller, double for long.
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//
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const Type* loadType = (srcSize <= 4)? Type::FloatTy : Type::DoubleTy;
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MachineInstr* load = new MachineInstr(ChooseLoadInstruction(loadType));
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load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
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load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,offset);
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load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
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mvec.push_back(load);
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mvec.push_back(BuildMI(ChooseLoadInstruction(loadType), 3)
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.addMReg(FPReg).addSImm(offset).addRegDef(dest));
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}
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// Similarly, create an instruction sequence to copy an FP register
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@ -543,14 +536,13 @@ UltraSparcInstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
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int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val);
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unsigned FPReg = target.getRegInfo().getFramePointer();
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// Store instruction stores `val' to [%fp+offset].
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// The store opCode is based only the source value being copied.
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//
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MachineInstr* store=new MachineInstr(ChooseStoreInstruction(opTy));
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store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, val);
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store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
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store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed,offset);
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mvec.push_back(store);
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mvec.push_back(BuildMI(ChooseStoreInstruction(opTy), 3)
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.addReg(val).addMReg(FPReg).addSImm(offset));
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// Load instruction loads [%fp+offset] to `dest'.
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// The type of the load opCode is the integer type that matches the
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@ -560,11 +552,8 @@ UltraSparcInstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
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// ensure correct sign-extension for UByte, UShort or UInt:
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//
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const Type* loadTy = (opTy == Type::FloatTy)? Type::IntTy : Type::LongTy;
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MachineInstr* load = new MachineInstr(ChooseLoadInstruction(loadTy));
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load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
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load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,offset);
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load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
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mvec.push_back(load);
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mvec.push_back(BuildMI(ChooseLoadInstruction(loadTy), 3).addMReg(FPReg)
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.addSImm(offset).addRegDef(dest));
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}
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@ -26,6 +26,16 @@
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#include <math.h>
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using std::vector;
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static inline void Add3OperandInstr(unsigned Opcode, InstructionNode* Node,
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vector<MachineInstr*>& mvec) {
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mvec.push_back(BuildMI(Opcode, 3).addReg(Node->leftChild()->getValue())
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.addReg(Node->rightChild()->getValue())
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.addRegDef(Node->getValue()));
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}
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//************************ Internal Functions ******************************/
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@ -716,25 +726,26 @@ ChooseDivInstruction(TargetMachine &target,
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}
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// Return NULL if we cannot exploit constant to create a cheaper instruction
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// Return if we cannot exploit constant to create a cheaper instruction
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static inline void
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CreateDivConstInstruction(TargetMachine &target,
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const InstructionNode* instrNode,
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vector<MachineInstr*>& mvec)
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{
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MachineInstr* minstr1 = NULL;
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MachineInstr* minstr2 = NULL;
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Value* LHS = instrNode->leftChild()->getValue();
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Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
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if (! isa<Constant>(constOp))
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if (!isa<Constant>(constOp))
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return;
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Value* DestVal = instrNode->getValue();
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unsigned ZeroReg = target.getRegInfo().getZeroRegNum();
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// Cases worth optimizing are:
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// (1) Divide by 1 for any type: replace with copy (ADD or FMOV)
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// (2) Divide by 2^x for integer types: replace with SR[L or A]{X}
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//
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const Type* resultType = instrNode->getInstruction()->getType();
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if (resultType->isInteger())
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{
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unsigned pow;
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@ -743,39 +754,25 @@ CreateDivConstInstruction(TargetMachine &target,
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if (isValidConst)
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{
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bool needNeg = false;
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if (C < 0)
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{
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needNeg = true;
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C = -C;
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}
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if (C < 0) {
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needNeg = true;
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C = -C;
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}
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if (C == 1)
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{
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minstr1 = new MachineInstr(ADD);
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minstr1->SetMachineOperandVal(0,
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MachineOperand::MO_VirtualRegister,
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instrNode->leftChild()->getValue());
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minstr1->SetMachineOperandReg(1,
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target.getRegInfo().getZeroRegNum());
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}
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else if (isPowerOf2(C, pow))
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{
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MachineOpCode opCode= ((resultType->isSigned())
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? (resultType==Type::LongTy)? SRAX : SRA
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: (resultType==Type::LongTy)? SRLX : SRL);
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minstr1 = new MachineInstr(opCode);
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minstr1->SetMachineOperandVal(0,
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MachineOperand::MO_VirtualRegister,
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instrNode->leftChild()->getValue());
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minstr1->SetMachineOperandConst(1,
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MachineOperand::MO_UnextendedImmed,
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pow);
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}
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if (C == 1) {
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mvec.push_back(BuildMI(ADD, 3).addReg(LHS).addMReg(ZeroReg)
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.addRegDef(DestVal));
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} else if (isPowerOf2(C, pow)) {
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unsigned opCode= ((resultType->isSigned())
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? (resultType==Type::LongTy) ? SRAX : SRA
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: (resultType==Type::LongTy) ? SRLX : SRL);
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mvec.push_back(BuildMI(opCode, 3).addReg(LHS).addZImm(pow)
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.addRegDef(DestVal));
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}
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if (minstr1 && needNeg)
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if (needNeg && (C == 1 || isPowerOf2(C, pow)))
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{ // insert <reg = SUB 0, reg> after the instr to flip the sign
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minstr2 = CreateIntNegInstruction(target,
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instrNode->getValue());
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mvec.push_back(CreateIntNegInstruction(target, DestVal));
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}
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}
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}
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@ -786,28 +783,14 @@ CreateDivConstInstruction(TargetMachine &target,
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double dval = FPC->getValue();
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if (fabs(dval) == 1)
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{
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bool needNeg = (dval < 0);
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unsigned opCode =
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(dval < 0) ? (resultType == Type::FloatTy? FNEGS : FNEGD)
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: (resultType == Type::FloatTy? FMOVS : FMOVD);
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MachineOpCode opCode = needNeg
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? (resultType == Type::FloatTy? FNEGS : FNEGD)
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: (resultType == Type::FloatTy? FMOVS : FMOVD);
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minstr1 = new MachineInstr(opCode);
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minstr1->SetMachineOperandVal(0,
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MachineOperand::MO_VirtualRegister,
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instrNode->leftChild()->getValue());
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mvec.push_back(BuildMI(opCode, 2).addReg(LHS).addRegDef(DestVal));
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}
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}
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}
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if (minstr1 != NULL)
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minstr1->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
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instrNode->getValue());
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if (minstr1)
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mvec.push_back(minstr1);
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if (minstr2)
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mvec.push_back(minstr2);
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}
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@ -870,20 +853,15 @@ CreateCodeForVariableSizeAlloca(const TargetMachine& target,
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target.getFrameInfo().getDynamicAreaOffset(mcInfo,growUp));
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assert(! growUp && "Has SPARC v9 stack frame convention changed?");
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unsigned SPReg = target.getRegInfo().getStackPointer();
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// Instruction 2: sub %sp, totalSizeVal -> %sp
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M = new MachineInstr(SUB);
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M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
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M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, totalSizeVal);
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M->SetMachineOperandReg(2, target.getRegInfo().getStackPointer());
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getMvec.push_back(M);
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getMvec.push_back(BuildMI(SUB, 3).addMReg(SPReg).addReg(totalSizeVal)
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.addMReg(SPReg,MOTy::Def));
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// Instruction 3: add %sp, frameSizeBelowDynamicArea -> result
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M = new MachineInstr(ADD);
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M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
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M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
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dynamicAreaOffset);
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M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result);
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getMvec.push_back(M);
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getMvec.push_back(BuildMI(ADD, 3).addMReg(SPReg).addReg(dynamicAreaOffset)
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.addRegDef(result));
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}
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@ -923,12 +901,9 @@ CreateCodeForFixedSizeAlloca(const TargetMachine& target,
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ConstantSInt* offsetVal = ConstantSInt::get(Type::IntTy, offsetFromFP);
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// Instruction 1: add %fp, offsetFromFP -> result
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MachineInstr* M = new MachineInstr(ADD);
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M->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
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M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, offsetVal);
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M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result);
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getMvec.push_back(M);
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unsigned FPReg = target.getRegInfo().getFramePointer();
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getMvec.push_back(BuildMI(ADD, 3).addMReg(FPReg).addReg(offsetVal)
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.addRegDef(result));
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}
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@ -949,13 +924,12 @@ CreateCodeForFixedSizeAlloca(const TargetMachine& target,
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//------------------------------------------------------------------------
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static void
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SetOperandsForMemInstr(vector<MachineInstr*>& mvec,
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SetOperandsForMemInstr(unsigned Opcode,
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vector<MachineInstr*>& mvec,
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InstructionNode* vmInstrNode,
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const TargetMachine& target)
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{
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Instruction* memInst = vmInstrNode->getInstruction();
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vector<MachineInstr*>::iterator mvecI = mvec.end() - 1;
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// Index vector, ptr value, and flag if all indices are const.
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vector<Value*> idxVec;
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bool allConstantIndices;
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@ -1020,12 +994,8 @@ SetOperandsForMemInstr(vector<MachineInstr*>& mvec,
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mulVec, MachineCodeForInstruction::get(memInst),
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INVALID_MACHINE_OPCODE);
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// Insert mulVec[] before *mvecI in mvec[] and update mvecI
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// to point to the same instruction it pointed to before.
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assert(mulVec.size() > 0 && "No multiply code created?");
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vector<MachineInstr*>::iterator oldMvecI = mvecI;
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for (unsigned i=0, N=mulVec.size(); i < N; ++i)
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mvecI = mvec.insert(mvecI, mulVec[i]) + 1; // pts to mem instr
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mvec.insert(mvec.end(), mulVec.begin(), mulVec.end());
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valueForRegOffset = addr;
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}
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@ -1042,33 +1012,23 @@ SetOperandsForMemInstr(vector<MachineInstr*>& mvec,
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// Operand 0 is ptr, operand 1 is offset, operand 2 is result.
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//
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unsigned offsetOpNum, ptrOpNum;
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if (memInst->getOpcode() == Instruction::Store)
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{
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(*mvecI)->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
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vmInstrNode->leftChild()->getValue());
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ptrOpNum = 1;
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offsetOpNum = 2;
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}
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else
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{
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ptrOpNum = 0;
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offsetOpNum = 1;
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(*mvecI)->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
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memInst);
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}
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(*mvecI)->SetMachineOperandVal(ptrOpNum, MachineOperand::MO_VirtualRegister,
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ptrVal);
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if (offsetOpType == MachineOperand::MO_VirtualRegister)
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{
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assert(valueForRegOffset != NULL);
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(*mvecI)->SetMachineOperandVal(offsetOpNum, offsetOpType,
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valueForRegOffset);
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}
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else
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(*mvecI)->SetMachineOperandConst(offsetOpNum, offsetOpType,
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smallConstOffset);
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MachineInstr *MI;
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if (memInst->getOpcode() == Instruction::Store) {
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if (offsetOpType == MachineOperand::MO_VirtualRegister)
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MI = BuildMI(Opcode, 3).addReg(vmInstrNode->leftChild()->getValue())
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.addReg(ptrVal).addReg(valueForRegOffset);
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else
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MI = BuildMI(Opcode, 3).addReg(vmInstrNode->leftChild()->getValue())
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.addReg(ptrVal).addSImm(smallConstOffset);
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} else {
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if (offsetOpType == MachineOperand::MO_VirtualRegister)
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MI = BuildMI(Opcode, 3).addReg(ptrVal).addReg(valueForRegOffset)
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.addRegDef(memInst);
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else
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MI = BuildMI(Opcode, 3).addReg(ptrVal).addSImm(smallConstOffset)
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.addRegDef(memInst);
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}
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mvec.push_back(MI);
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}
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@ -1265,21 +1225,20 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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case 3: // stmt: Store(reg,reg)
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case 4: // stmt: Store(reg,ptrreg)
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mvec.push_back(new MachineInstr(
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ChooseStoreInstruction(
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subtreeRoot->leftChild()->getValue()->getType())));
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SetOperandsForMemInstr(mvec, subtreeRoot, target);
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SetOperandsForMemInstr(ChooseStoreInstruction(
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subtreeRoot->leftChild()->getValue()->getType()),
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mvec, subtreeRoot, target);
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break;
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case 5: // stmt: BrUncond
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M = new MachineInstr(BA);
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M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
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cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(0));
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mvec.push_back(M);
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{
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BranchInst *BI = cast<BranchInst>(subtreeRoot->getInstruction());
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mvec.push_back(BuildMI(BA, 1).addPCDisp(BI->getSuccessor(0)));
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// delay slot
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mvec.push_back(new MachineInstr(NOP));
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break;
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// delay slot
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mvec.push_back(BuildMI(NOP, 0));
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break;
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}
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case 206: // stmt: BrCond(setCCconst)
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{ // setCCconst => boolean was computed with `%b = setCC type reg1 const'
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@ -1308,25 +1267,19 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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BranchInst* brInst=cast<BranchInst>(subtreeRoot->getInstruction());
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M = new MachineInstr(ChooseBprInstruction(subtreeRoot));
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M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
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setCCNode->leftChild()->getValue());
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M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
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brInst->getSuccessor(0));
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M = BuildMI(ChooseBprInstruction(subtreeRoot), 2)
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.addReg(setCCNode->leftChild()->getValue())
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.addPCDisp(brInst->getSuccessor(0));
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mvec.push_back(M);
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// delay slot
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mvec.push_back(new MachineInstr(NOP));
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mvec.push_back(BuildMI(NOP, 0));
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// false branch
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M = new MachineInstr(BA);
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M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
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brInst->getSuccessor(1));
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mvec.push_back(M);
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mvec.push_back(BuildMI(BA, 1).addPCDisp(brInst->getSuccessor(1)));
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// delay slot
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mvec.push_back(new MachineInstr(NOP));
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mvec.push_back(BuildMI(NOP, 0));
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break;
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}
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// ELSE FALL THROUGH
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@ -1340,28 +1293,22 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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//
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BranchInst* brInst = cast<BranchInst>(subtreeRoot->getInstruction());
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bool isFPBranch;
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M = new MachineInstr(ChooseBccInstruction(subtreeRoot, isFPBranch));
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|
||||
unsigned Opcode = ChooseBccInstruction(subtreeRoot, isFPBranch);
|
||||
Value* ccValue = GetTmpForCC(subtreeRoot->leftChild()->getValue(),
|
||||
brInst->getParent()->getParent(),
|
||||
isFPBranch? Type::FloatTy : Type::IntTy);
|
||||
|
||||
M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister, ccValue);
|
||||
M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
|
||||
brInst->getSuccessor(0));
|
||||
M = BuildMI(Opcode, 2).addCCReg(ccValue)
|
||||
.addPCDisp(brInst->getSuccessor(0));
|
||||
mvec.push_back(M);
|
||||
|
||||
// delay slot
|
||||
mvec.push_back(new MachineInstr(NOP));
|
||||
mvec.push_back(BuildMI(NOP, 0));
|
||||
|
||||
// false branch
|
||||
M = new MachineInstr(BA);
|
||||
M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
|
||||
brInst->getSuccessor(1));
|
||||
mvec.push_back(M);
|
||||
mvec.push_back(BuildMI(BA, 1).addPCDisp(brInst->getSuccessor(1)));
|
||||
|
||||
// delay slot
|
||||
mvec.push_back(new MachineInstr(NOP));
|
||||
mvec.push_back(BuildMI(NOP, 0));
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1372,13 +1319,12 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
cast<Constant>(subtreeRoot->leftChild()->getValue());
|
||||
unsigned dest = cast<ConstantBool>(constVal)->getValue()? 0 : 1;
|
||||
|
||||
M = new MachineInstr(BA);
|
||||
M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
|
||||
M = BuildMI(BA, 1).addPCDisp(
|
||||
cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(dest));
|
||||
mvec.push_back(M);
|
||||
|
||||
// delay slot
|
||||
mvec.push_back(new MachineInstr(NOP));
|
||||
mvec.push_back(BuildMI(NOP, 0));
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1386,24 +1332,19 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
{ // boolreg => boolean is stored in an existing register.
|
||||
// Just use the branch-on-integer-register instruction!
|
||||
//
|
||||
M = new MachineInstr(BRNZ);
|
||||
M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
|
||||
subtreeRoot->leftChild()->getValue());
|
||||
M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
|
||||
cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(0));
|
||||
BranchInst *BI = cast<BranchInst>(subtreeRoot->getInstruction());
|
||||
M = BuildMI(BRNZ, 2).addReg(subtreeRoot->leftChild()->getValue())
|
||||
.addPCDisp(BI->getSuccessor(0));
|
||||
mvec.push_back(M);
|
||||
|
||||
// delay slot
|
||||
mvec.push_back(new MachineInstr(NOP));
|
||||
mvec.push_back(BuildMI(NOP, 0));
|
||||
|
||||
// false branch
|
||||
M = new MachineInstr(BA);
|
||||
M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
|
||||
cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(1));
|
||||
mvec.push_back(M);
|
||||
mvec.push_back(BuildMI(BA, 1).addPCDisp(BI->getSuccessor(1)));
|
||||
|
||||
// delay slot
|
||||
mvec.push_back(new MachineInstr(NOP));
|
||||
mvec.push_back(BuildMI(NOP, 0));
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1589,11 +1530,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
else
|
||||
srcForCast = leftVal;
|
||||
|
||||
M = new MachineInstr(opCode);
|
||||
M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
|
||||
srcForCast);
|
||||
M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
|
||||
dest);
|
||||
M = BuildMI(opCode, 2).addReg(srcForCast).addRegDef(dest);
|
||||
mvec.push_back(M);
|
||||
}
|
||||
}
|
||||
@ -1616,8 +1553,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
|
||||
case 33: // reg: Add(reg, reg)
|
||||
maskUnsignedResult = true;
|
||||
mvec.push_back(new MachineInstr(ChooseAddInstruction(subtreeRoot)));
|
||||
Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
|
||||
Add3OperandInstr(ChooseAddInstruction(subtreeRoot), subtreeRoot, mvec);
|
||||
break;
|
||||
|
||||
case 234: // reg: Sub(reg, Constant)
|
||||
@ -1632,9 +1568,9 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
|
||||
case 34: // reg: Sub(reg, reg)
|
||||
maskUnsignedResult = true;
|
||||
mvec.push_back(new MachineInstr(ChooseSubInstructionByType(
|
||||
subtreeRoot->getInstruction()->getType())));
|
||||
Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
|
||||
Add3OperandInstr(ChooseSubInstructionByType(
|
||||
subtreeRoot->getInstruction()->getType()),
|
||||
subtreeRoot, mvec);
|
||||
break;
|
||||
|
||||
case 135: // reg: Mul(todouble, todouble)
|
||||
@ -1684,9 +1620,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
|
||||
case 36: // reg: Div(reg, reg)
|
||||
maskUnsignedResult = true;
|
||||
mvec.push_back(new MachineInstr(ChooseDivInstruction(target,
|
||||
subtreeRoot)));
|
||||
Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
|
||||
Add3OperandInstr(ChooseDivInstruction(target, subtreeRoot),
|
||||
subtreeRoot, mvec);
|
||||
break;
|
||||
|
||||
case 37: // reg: Rem(reg, reg)
|
||||
@ -1703,9 +1638,10 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
subtreeRoot->rightChild()->getValue());
|
||||
MachineCodeForInstruction::get(remInstr).addTemp(quot).addTemp(prod);
|
||||
|
||||
M = new MachineInstr(ChooseDivInstruction(target, subtreeRoot));
|
||||
Set3OperandsFromInstr(M, subtreeRoot, target);
|
||||
M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,quot);
|
||||
M = BuildMI(ChooseDivInstruction(target, subtreeRoot), 3)
|
||||
.addReg(subtreeRoot->leftChild()->getValue())
|
||||
.addReg(subtreeRoot->rightChild()->getValue())
|
||||
.addRegDef(quot);
|
||||
mvec.push_back(M);
|
||||
|
||||
unsigned MulOpcode =
|
||||
@ -1715,12 +1651,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
MOTy::Def);
|
||||
mvec.push_back(M);
|
||||
|
||||
M = new MachineInstr(ChooseSubInstructionByType(
|
||||
subtreeRoot->getInstruction()->getType()));
|
||||
Set3OperandsFromInstr(M, subtreeRoot, target);
|
||||
M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,prod);
|
||||
unsigned Opcode = ChooseSubInstructionByType(
|
||||
subtreeRoot->getInstruction()->getType());
|
||||
M = BuildMI(Opcode, 3).addReg(subtreeRoot->leftChild()->getValue())
|
||||
.addReg(prod).addRegDef(subtreeRoot->getValue());
|
||||
mvec.push_back(M);
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1728,8 +1663,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
case 238: // bool: And(bool, boolconst)
|
||||
case 338: // reg : BAnd(reg, reg)
|
||||
case 538: // reg : BAnd(reg, Constant)
|
||||
mvec.push_back(new MachineInstr(AND));
|
||||
Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
|
||||
Add3OperandInstr(AND, subtreeRoot, mvec);
|
||||
break;
|
||||
|
||||
case 138: // bool: And(bool, not)
|
||||
@ -1751,8 +1685,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
case 239: // bool: Or(bool, boolconst)
|
||||
case 339: // reg : BOr(reg, reg)
|
||||
case 539: // reg : BOr(reg, Constant)
|
||||
mvec.push_back(new MachineInstr(OR));
|
||||
Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
|
||||
Add3OperandInstr(OR, subtreeRoot, mvec);
|
||||
break;
|
||||
|
||||
case 139: // bool: Or(bool, not)
|
||||
@ -1774,8 +1707,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
case 240: // bool: Xor(bool, boolconst)
|
||||
case 340: // reg : BXor(reg, reg)
|
||||
case 540: // reg : BXor(reg, Constant)
|
||||
mvec.push_back(new MachineInstr(XOR));
|
||||
Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
|
||||
Add3OperandInstr(XOR, subtreeRoot, mvec);
|
||||
break;
|
||||
|
||||
case 140: // bool: Xor(bool, not)
|
||||
@ -1854,10 +1786,17 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
// a separate instruction to compute the bool result, so discard
|
||||
// result of SUBcc instruction anyway.
|
||||
//
|
||||
M = new MachineInstr(SUBcc);
|
||||
Set3OperandsFromInstr(M, subtreeRoot, target, ! keepSubVal);
|
||||
M->SetMachineOperandVal(3, MachineOperand::MO_CCRegister,
|
||||
tmpForCC, /*def*/true);
|
||||
if (keepSubVal) {
|
||||
M = BuildMI(SUBcc, 4).addReg(subtreeRoot->leftChild()->getValue())
|
||||
.addReg(subtreeRoot->rightChild()->getValue())
|
||||
.addRegDef(subtreeRoot->getValue())
|
||||
.addCCReg(tmpForCC, MOTy::Def);
|
||||
} else {
|
||||
M = BuildMI(SUBcc, 4).addReg(subtreeRoot->leftChild()->getValue())
|
||||
.addReg(subtreeRoot->rightChild()->getValue())
|
||||
.addMReg(target.getRegInfo().getZeroRegNum(), MOTy::Def)
|
||||
.addCCReg(tmpForCC, MOTy::Def);
|
||||
}
|
||||
mvec.push_back(M);
|
||||
|
||||
if (computeBoolVal)
|
||||
@ -1869,13 +1808,10 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
else
|
||||
{
|
||||
// FP condition: dest of FCMP should be some FCCn register
|
||||
M = new MachineInstr(ChooseFcmpInstruction(subtreeRoot));
|
||||
M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
|
||||
tmpForCC);
|
||||
M->SetMachineOperandVal(1,MachineOperand::MO_VirtualRegister,
|
||||
subtreeRoot->leftChild()->getValue());
|
||||
M->SetMachineOperandVal(2,MachineOperand::MO_VirtualRegister,
|
||||
subtreeRoot->rightChild()->getValue());
|
||||
M = BuildMI(ChooseFcmpInstruction(subtreeRoot), 3)
|
||||
.addCCReg(tmpForCC, MOTy::Def)
|
||||
.addReg(subtreeRoot->leftChild()->getValue())
|
||||
.addRegDef(subtreeRoot->rightChild()->getValue());
|
||||
mvec.push_back(M);
|
||||
|
||||
if (computeBoolVal)
|
||||
@ -1890,25 +1826,15 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
{
|
||||
if (mustClearReg)
|
||||
{// Unconditionally set register to 0
|
||||
M = new MachineInstr(SETHI);
|
||||
M->SetMachineOperandConst(0,MachineOperand::MO_UnextendedImmed,
|
||||
(int64_t)0);
|
||||
M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
|
||||
setCCInstr);
|
||||
M = BuildMI(SETHI, 2).addZImm(0).addRegDef(setCCInstr);
|
||||
mvec.push_back(M);
|
||||
}
|
||||
|
||||
// Now conditionally move `valueToMove' (0 or 1) into the register
|
||||
// Mark the register as a use (as well as a def) because the old
|
||||
// value should be retained if the condition is false.
|
||||
M = new MachineInstr(movOpCode);
|
||||
M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
|
||||
tmpForCC);
|
||||
M->SetMachineOperandConst(1, MachineOperand::MO_UnextendedImmed,
|
||||
valueToMove);
|
||||
M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
|
||||
setCCInstr, /*isDef*/ true,
|
||||
/*isDefAndUse*/ true);
|
||||
M = BuildMI(movOpCode, 3).addCCReg(tmpForCC).addZImm(valueToMove)
|
||||
.addReg(setCCInstr, MOTy::UseAndDef);
|
||||
mvec.push_back(M);
|
||||
}
|
||||
break;
|
||||
@ -1916,17 +1842,16 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
|
||||
case 51: // reg: Load(reg)
|
||||
case 52: // reg: Load(ptrreg)
|
||||
mvec.push_back(new MachineInstr(ChooseLoadInstruction(
|
||||
subtreeRoot->getValue()->getType())));
|
||||
SetOperandsForMemInstr(mvec, subtreeRoot, target);
|
||||
SetOperandsForMemInstr(ChooseLoadInstruction(
|
||||
subtreeRoot->getValue()->getType()),
|
||||
mvec, subtreeRoot, target);
|
||||
break;
|
||||
|
||||
case 55: // reg: GetElemPtr(reg)
|
||||
case 56: // reg: GetElemPtrIdx(reg,reg)
|
||||
// If the GetElemPtr was folded into the user (parent), it will be
|
||||
// caught above. For other cases, we have to compute the address.
|
||||
mvec.push_back(new MachineInstr(ADD));
|
||||
SetOperandsForMemInstr(mvec, subtreeRoot, target);
|
||||
SetOperandsForMemInstr(ADD, mvec, subtreeRoot, target);
|
||||
break;
|
||||
|
||||
case 57: // reg: Alloca: Implement as 1 instruction:
|
||||
@ -2069,7 +1994,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
mvec.back()->addImplicitRef(retAddrReg, /*isDef*/ true);
|
||||
|
||||
// delay slot
|
||||
mvec.push_back(new MachineInstr(NOP));
|
||||
mvec.push_back(BuildMI(NOP, 0));
|
||||
break;
|
||||
}
|
||||
|
||||
@ -2094,10 +2019,10 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
{ const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
|
||||
assert((opType->isInteger() || isa<PointerType>(opType)) &&
|
||||
"Shr unsupported for other types");
|
||||
mvec.push_back(new MachineInstr((opType->isSigned()
|
||||
? ((opType == Type::LongTy)? SRAX : SRA)
|
||||
: ((opType == Type::LongTy)? SRLX : SRL))));
|
||||
Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
|
||||
Add3OperandInstr(opType->isSigned()
|
||||
? (opType == Type::LongTy ? SRAX : SRA)
|
||||
: (opType == Type::LongTy ? SRLX : SRL),
|
||||
subtreeRoot, mvec);
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user