RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-11-25 12:50:00 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Make the 'x' constraint work for AVX registers as well.

Browse Source 
Fixes rdar://10614894

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147704 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2012-01-07 01:02:09 +00:00
parent 9c7b3da04a
commit 5548755201
2 changed files with 22 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
lib/Target/X86/X86ISelLowering.cpp
View File

@ -15098,7 +15098,8 @@ TargetLowering::ConstraintWeight
break;
case 'x':
case 'Y':
if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM()) ||
((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
weight = CW_Register;
break;
case 'I':
@ -15378,8 +15379,8 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
case 'Y': // SSE_REGS if SSE2 allowed
if (!Subtarget->hasXMMInt()) break;
// FALL THROUGH.
case 'x': // SSE_REGS if SSE1 allowed
if (!Subtarget->hasXMM()) break;
case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
if (!Subtarget->hasXMM() && !Subtarget->hasAVX()) break;
switch (VT.getSimpleVT().SimpleTy) {
default: break;
@ -15398,6 +15399,15 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
case MVT::v4f32:
case MVT::v2f64:
return std::make_pair(0U, X86::VR128RegisterClass);
// AVX types.
case MVT::v32i8:
case MVT::v16i16:
case MVT::v8i32:
case MVT::v4i64:
case MVT::v8f32:
case MVT::v4f64:
return std::make_pair(0U, X86::VR256RegisterClass);
}
break;
}

10
test/CodeGen/X86/inline-asm-q-regs.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64
; RUN: llc < %s -march=x86-64 -mattr=+avx
; rdar://7066579
%0 = type { i64, i64, i64, i64, i64 } ; type %0
@ -27,3 +27,11 @@ entry:
%0 = tail call { i8, i8, i8, i8, i8 } asm "foo $1, $2, $3, $4, $1\0Axchgb ${0:b}, ${0:h}", "=q,={ax},={bx},={cx},={dx},0,1,2,3,4,~{dirflag},~{fpsr},~{flags}"(i8 %val, i8 %a, i8 %b, i8 %c, i8 %d) nounwind
ret void
}
; rdar://10614894
define <8 x float> @test5(<8 x float> %a, <8 x float> %b) nounwind {
entry:
%0 = tail call <8 x float> asm "vperm2f128 $3, $2, $1, $0", "=x,x,x,i,~{dirflag},~{fpsr},~{flags}"(<8 x float> %a, <8 x float> %b, i32 16) nounwind
ret <8 x float> %0
}