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These methods no longer take a TargetRegisterClass* operand.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15774 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-08-15 21:56:44 +00:00
parent ed6655920f
commit 57f1b67c34
16 changed files with 58 additions and 86 deletions
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9
lib/CodeGen/PrologEpilogInserter.cpp
View File

@ -206,10 +206,8 @@ void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
MachineBasicBlock *MBB = Fn.begin();
MachineBasicBlock::iterator I = MBB->begin();
for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) {
const TargetRegisterClass *RC = RegInfo->getRegClass(RegsToSave[i]);
// Insert the spill to the stack frame...
RegInfo->storeRegToStackSlot(*MBB, I, RegsToSave[i], StackSlots[i], RC);
// Insert the spill to the stack frame.
RegInfo->storeRegToStackSlot(*MBB, I, RegsToSave[i], StackSlots[i]);
}
// Add code to restore the callee-save registers in each exiting block.
@ -221,8 +219,7 @@ void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
I = MBB->end(); --I;
for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) {
const TargetRegisterClass *RC = RegInfo->getRegClass(RegsToSave[i]);
RegInfo->loadRegFromStackSlot(*MBB, I, RegsToSave[i],StackSlots[i], RC);
RegInfo->loadRegFromStackSlot(*MBB, I, RegsToSave[i],StackSlots[i]);
--I; // Insert in reverse order
}
}

4
lib/CodeGen/RegAllocLocal.cpp
View File

@ -267,7 +267,7 @@ void RA::spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
int FrameIndex = getStackSpaceFor(VirtReg, RC);
DEBUG(std::cerr << " to stack slot #" << FrameIndex);
RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC);
RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex);
++NumStores; // Update statistics
}
@ -506,7 +506,7 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
<< RegInfo->getName(PhysReg) << "\n");
// Add move instruction(s)
RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex);
++NumLoads; // Update statistics
MI->SetMachineOperandReg(OpNum, PhysReg); // Assign the input register

4
lib/CodeGen/RegAllocSimple.cpp
View File

@ -131,7 +131,7 @@ unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
// Add move instruction(s)
++NumLoads;
RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx);
return PhysReg;
}
@ -143,7 +143,7 @@ void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
// Add move instruction(s)
++NumStores;
RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC);
RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx);
}

12
lib/CodeGen/VirtRegMap.cpp
View File

@ -144,8 +144,7 @@ namespace {
*mbbi,
mii,
physReg,
vrm.getStackSlot(virtReg),
mf.getSSARegMap()->getRegClass(virtReg));
vrm.getStackSlot(virtReg));
loaded[virtReg] = true;
DEBUG(std::cerr << '\t';
prior(mii)->print(std::cerr, &tm));
@ -157,8 +156,7 @@ namespace {
*mbbi,
next(mii),
physReg,
vrm.getStackSlot(virtReg),
mf.getSSARegMap()->getRegClass(virtReg));
vrm.getStackSlot(virtReg));
++numStores;
}
mii->SetMachineOperandReg(i, physReg);
@ -226,8 +224,7 @@ namespace {
mri_->storeRegToStackSlot(*lastDef->getParent(),
nextLastRef,
physReg,
vrm_->getStackSlot(virtReg),
mri_->getRegClass(physReg));
vrm_->getStackSlot(virtReg));
++numStores;
DEBUG(std::cerr << "added: ";
prior(nextLastRef)->print(std::cerr, tm_);
@ -258,8 +255,7 @@ namespace {
// load if necessary
if (vrm_->hasStackSlot(virtReg)) {
mri_->loadRegFromStackSlot(mbb, mii, physReg,
vrm_->getStackSlot(virtReg),
mri_->getRegClass(physReg));
vrm_->getStackSlot(virtReg));
++numLoads;
DEBUG(std::cerr << "added: ";
prior(mii)->print(std::cerr, tm_));

9
lib/Target/PowerPC/PowerPCRegisterInfo.cpp
View File

@ -71,11 +71,12 @@ static unsigned getIdx(const TargetRegisterClass *RC) {
int
PowerPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const {
unsigned SrcReg, int FrameIdx) const {
const TargetRegisterClass *RC = getRegClass(SrcReg);
static const unsigned Opcode[] = {
PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD
};
unsigned OC = Opcode[getIdx(RC)];
if (SrcReg == PPC::LR) {
MBB.insert(MI, BuildMI(PPC::MFLR, 0, PPC::R0));
@ -91,11 +92,11 @@ PowerPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
int
PowerPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const {
unsigned DestReg, int FrameIdx) const{
static const unsigned Opcode[] = {
PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LD, PPC::LFS, PPC::LFD
};
const TargetRegisterClass *RC = getRegClass(DestReg);
unsigned OC = Opcode[getIdx(RC)];
if (DestReg == PPC::LR) {
MBB.insert(MI, addFrameReference(BuildMI(OC, 2, PPC::R0), FrameIdx));

6
lib/Target/PowerPC/PowerPCRegisterInfo.h
View File

@ -32,13 +32,11 @@ public:
/// Code Generation virtual methods...
int storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const;
unsigned SrcReg, int FrameIndex) const;
int loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const;
unsigned DestReg, int FrameIndex) const;
int copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned SrcReg,

14
lib/Target/Skeleton/SkeletonRegisterInfo.cpp
View File

@ -20,18 +20,16 @@ SkeletonRegisterInfo::SkeletonRegisterInfo()
: SkeletonGenRegisterInfo(Skeleton::ADJCALLSTACKDOWN,
Skeleton::ADJCALLSTACKUP) {}
int SkeletonRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const {
int SkeletonRegisterInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned SrcReg, int FrameIdx) const {
abort();
return -1;
}
int SkeletonRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const {
int SkeletonRegisterInfo::
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIdx) const {
abort();
return -1;
}

6
lib/Target/Skeleton/SkeletonRegisterInfo.h
View File

@ -27,13 +27,11 @@ namespace llvm {
// See MRegisterInfo.h for information on these methods.
int storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const;
unsigned SrcReg, int FrameIndex) const;
int loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const;
unsigned DestReg, int FrameIndex) const;
int copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned SrcReg,

21
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -25,12 +25,11 @@ SparcV8RegisterInfo::SparcV8RegisterInfo()
: SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
V8::ADJCALLSTACKUP) {}
int SparcV8RegisterInfo::storeRegToStackSlot(
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const
{
int SparcV8RegisterInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, int FrameIdx) const {
const TargetRegisterClass *RC = getRegClass(SrcReg);
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
if (RC == SparcV8::IntRegsRegisterClass)
BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
@ -46,12 +45,10 @@ int SparcV8RegisterInfo::storeRegToStackSlot(
return 1;
}
int SparcV8RegisterInfo::loadRegFromStackSlot(
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const
{
int SparcV8RegisterInfo::
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, int FrameIdx) const {
const TargetRegisterClass *RC = getRegClass(DestReg);
if (RC == SparcV8::IntRegsRegisterClass)
BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
else if (RC == SparcV8::FPRegsRegisterClass)

6
lib/Target/Sparc/SparcRegisterInfo.h
View File

@ -28,13 +28,11 @@ struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
/// Code Generation virtual methods...
int storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const;
unsigned SrcReg, int FrameIndex) const;
int loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const;
unsigned DestReg, int FrameIndex) const;
int copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned SrcReg,

21
lib/Target/SparcV8/SparcV8RegisterInfo.cpp
View File

@ -25,12 +25,11 @@ SparcV8RegisterInfo::SparcV8RegisterInfo()
: SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
V8::ADJCALLSTACKUP) {}
int SparcV8RegisterInfo::storeRegToStackSlot(
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const
{
int SparcV8RegisterInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, int FrameIdx) const {
const TargetRegisterClass *RC = getRegClass(SrcReg);
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
if (RC == SparcV8::IntRegsRegisterClass)
BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
@ -46,12 +45,10 @@ int SparcV8RegisterInfo::storeRegToStackSlot(
return 1;
}
int SparcV8RegisterInfo::loadRegFromStackSlot(
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const
{
int SparcV8RegisterInfo::
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, int FrameIdx) const {
const TargetRegisterClass *RC = getRegClass(DestReg);
if (RC == SparcV8::IntRegsRegisterClass)
BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
else if (RC == SparcV8::FPRegsRegisterClass)

6
lib/Target/SparcV8/SparcV8RegisterInfo.h
View File

@ -28,13 +28,11 @@ struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
/// Code Generation virtual methods...
int storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const;
unsigned SrcReg, int FrameIndex) const;
int loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const;
unsigned DestReg, int FrameIndex) const;
int copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned SrcReg,

6
lib/Target/SparcV9/SparcV9RegisterInfo.cpp
View File

@ -278,15 +278,13 @@ SparcV9RegisterInfo::SparcV9RegisterInfo ()
int SparcV9RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const {
unsigned SrcReg, int FrameIndex) const{
abort ();
}
int SparcV9RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const {
unsigned DestReg, int FrameIndex) const {
abort ();
}

6
lib/Target/SparcV9/SparcV9RegisterInfo.h
View File

@ -27,12 +27,10 @@ struct SparcV9RegisterInfo : public MRegisterInfo {
// The rest of these are stubs... for now.
int storeRegToStackSlot (MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const;
unsigned SrcReg, int FrameIndex) const;
int loadRegFromStackSlot (MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const;
unsigned DestReg, int FrameIndex) const;
int copyRegToReg (MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,

8
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -56,10 +56,10 @@ static unsigned getIdx(const TargetRegisterClass *RC) {
int X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const {
unsigned SrcReg, int FrameIdx) const {
static const unsigned Opcode[] =
{ X86::MOV8mr, X86::MOV16mr, X86::MOV32mr, X86::FSTP80m };
const TargetRegisterClass *RC = getRegClass(SrcReg);
MachineInstr *I = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
FrameIdx).addReg(SrcReg);
MBB.insert(MI, I);
@ -68,10 +68,10 @@ int X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
int X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const{
unsigned DestReg, int FrameIdx) const{
static const unsigned Opcode[] =
{ X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD80m };
const TargetRegisterClass *RC = getRegClass(DestReg);
unsigned OC = Opcode[getIdx(RC)];
MBB.insert(MI, addFrameReference(BuildMI(OC, 4, DestReg), FrameIdx));
return 1;

6
lib/Target/X86/X86RegisterInfo.h
View File

@ -29,13 +29,11 @@ struct X86RegisterInfo : public X86GenRegisterInfo {
/// Code Generation virtual methods...
int storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const;
unsigned SrcReg, int FrameIndex) const;
int loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const;
unsigned DestReg, int FrameIndex) const;
int copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,