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https://github.com/RPCSX/llvm.git
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Generalize ExtendUsesToFormExtLoad to be usable for ANY_EXTEND,
in addition to ZERO_EXTEND and SIGN_EXTEND. Fix a bug in the way it checked for live-out values, and simplify the way it find users by using SDNode::use_iterator's (relatively) new features. Also, make it slightly more permissive on targets with free truncates. In SelectionDAGBuild, avoid creating ANY_EXTEND nodes that are larger than necessary. If the target's SwitchAmountTy has enough bits, use it. This exposes the truncate to optimization early, enabling more optimizations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68670 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
parent
7d770be047
commit
57fc82d409
@ -2874,7 +2874,7 @@ SDValue DAGCombiner::visitSETCC(SDNode *N) {
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}
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// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
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// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))"
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// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
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// transformation. Returns true if extension are possible and the above
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// mentioned transformation is profitable.
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static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
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@ -2889,8 +2889,10 @@ static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
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SDNode *User = *UI;
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if (User == N)
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continue;
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if (UI.getUse().getResNo() != N0.getResNo())
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continue;
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// FIXME: Only extend SETCC N, N and SETCC N, c for now.
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if (User->getOpcode() == ISD::SETCC) {
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if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
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ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
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if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
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// Sign bits will be lost after a zext.
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@ -2906,32 +2908,25 @@ static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
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}
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if (Add)
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ExtendNodes.push_back(User);
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} else {
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for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
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SDValue UseOp = User->getOperand(i);
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if (UseOp == N0) {
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// If truncate from extended type to original load type is free
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// on this target, then it's ok to extend a CopyToReg.
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if (isTruncFree && User->getOpcode() == ISD::CopyToReg)
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HasCopyToRegUses = true;
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else
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return false;
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}
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}
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continue;
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}
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// If truncates aren't free and there are users we can't
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// extend, it isn't worthwhile.
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if (!isTruncFree)
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return false;
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// Remember if this value is live-out.
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if (User->getOpcode() == ISD::CopyToReg)
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HasCopyToRegUses = true;
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}
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if (HasCopyToRegUses) {
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bool BothLiveOut = false;
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for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
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UI != UE; ++UI) {
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SDNode *User = *UI;
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for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
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SDValue UseOp = User->getOperand(i);
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if (UseOp.getNode() == N && UseOp.getResNo() == 0) {
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BothLiveOut = true;
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break;
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}
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SDUse &Use = UI.getUse();
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if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
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BothLiveOut = true;
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break;
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}
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}
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if (BothLiveOut)
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@ -3013,8 +3008,8 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
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if (DoXform) {
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LoadSDNode *LN0 = cast<LoadSDNode>(N0);
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SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(),
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VT, LN0->getChain(),
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SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
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LN0->getChain(),
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LN0->getBasePtr(), LN0->getSrcValue(),
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LN0->getSrcValueOffset(),
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N0.getValueType(),
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@ -3034,8 +3029,8 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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if (SOp == Trunc)
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Ops.push_back(ExtLoad);
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else
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Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
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VT, SOp));
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Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND,
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N->getDebugLoc(), VT, SOp));
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}
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Ops.push_back(SetCC->getOperand(2));
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@ -3278,26 +3273,48 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
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}
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// fold (aext (load x)) -> (aext (truncate (extload x)))
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if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
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if (ISD::isNON_EXTLoad(N0.getNode()) &&
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((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
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TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
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LoadSDNode *LN0 = cast<LoadSDNode>(N0);
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SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
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LN0->getChain(),
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LN0->getBasePtr(), LN0->getSrcValue(),
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LN0->getSrcValueOffset(),
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N0.getValueType(),
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LN0->isVolatile(), LN0->getAlignment());
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CombineTo(N, ExtLoad);
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// Redirect any chain users to the new load.
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DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1),
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SDValue(ExtLoad.getNode(), 1));
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// If any node needs the original loaded value, recompute it.
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if (!LN0->use_empty())
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CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
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N0.getValueType(), ExtLoad),
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ExtLoad.getValue(1));
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return SDValue(N, 0); // Return N so it doesn't get rechecked!
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bool DoXform = true;
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SmallVector<SDNode*, 4> SetCCs;
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if (!N0.hasOneUse())
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DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
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if (DoXform) {
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LoadSDNode *LN0 = cast<LoadSDNode>(N0);
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SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
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LN0->getChain(),
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LN0->getBasePtr(), LN0->getSrcValue(),
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LN0->getSrcValueOffset(),
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N0.getValueType(),
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LN0->isVolatile(), LN0->getAlignment());
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CombineTo(N, ExtLoad);
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SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
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N0.getValueType(), ExtLoad);
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CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
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// Extend SetCC uses if necessary.
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for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
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SDNode *SetCC = SetCCs[i];
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SmallVector<SDValue, 4> Ops;
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for (unsigned j = 0; j != 2; ++j) {
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SDValue SOp = SetCC->getOperand(j);
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if (SOp == Trunc)
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Ops.push_back(ExtLoad);
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else
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Ops.push_back(DAG.getNode(ISD::ANY_EXTEND,
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N->getDebugLoc(), VT, SOp));
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}
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Ops.push_back(SetCC->getOperand(2));
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CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
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SetCC->getValueType(0),
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&Ops[0], Ops.size()));
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}
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return SDValue(N, 0); // Return N so it doesn't get rechecked!
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}
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}
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// fold (aext (zextload x)) -> (aext (truncate (zextload x)))
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@ -2190,8 +2190,24 @@ void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
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void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
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SDValue Op1 = getValue(I.getOperand(0));
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SDValue Op2 = getValue(I.getOperand(1));
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if (!isa<VectorType>(I.getType())) {
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if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
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if (!isa<VectorType>(I.getType()) &&
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Op2.getValueType() != TLI.getShiftAmountTy()) {
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// If the operand is smaller than the shift count type, promote it.
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if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
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Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
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TLI.getShiftAmountTy(), Op2);
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// If the operand is larger than the shift count type but the shift
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// count type has enough bits to represent any shift value, truncate
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// it now. This is a common case and it exposes the truncate to
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// optimization early.
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else if (TLI.getShiftAmountTy().getSizeInBits() >=
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Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
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Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
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TLI.getShiftAmountTy(), Op2);
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// Otherwise we'll need to temporarily settle for some other
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// convenient type; type legalization will make adjustments as
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// needed.
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else if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
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Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
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TLI.getPointerTy(), Op2);
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else if (TLI.getPointerTy().bitsGT(Op2.getValueType()))
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@ -1,40 +0,0 @@
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; RUN: llvm-as < %s | llc -march=x86 | grep movw | not grep %e.x
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; PR2681
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@g_491 = external global i32 ; <i32*> [#uses=1]
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@g_897 = external global i16 ; <i16*> [#uses=1]
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define i32 @func_7(i16 signext %p_9) nounwind {
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entry:
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%p_9.addr = alloca i16 ; <i16*> [#uses=2]
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%l_1122 = alloca i16, align 2 ; <i16*> [#uses=1]
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%l_1128 = alloca i32, align 4 ; <i32*> [#uses=1]
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%l_1129 = alloca i32, align 4 ; <i32*> [#uses=1]
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%l_1130 = alloca i32, align 4 ; <i32*> [#uses=1]
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%tmp14 = load i16* %l_1122 ; <i16> [#uses=1]
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%conv15 = sext i16 %tmp14 to i32 ; <i32> [#uses=1]
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%tmp16 = load i16* %p_9.addr ; <i16> [#uses=1]
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%conv17 = sext i16 %tmp16 to i32 ; <i32> [#uses=1]
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%xor = xor i32 %conv15, %conv17 ; <i32> [#uses=1]
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%tmp18 = load i32* null ; <i32> [#uses=1]
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%or = or i32 %xor, %tmp18 ; <i32> [#uses=1]
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%conv19 = trunc i32 %or to i16 ; <i16> [#uses=1]
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%tmp28 = load i16* %p_9.addr ; <i16> [#uses=1]
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%tmp33 = load i16* @g_897 ; <i16> [#uses=1]
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%tmp34 = load i32* @g_491 ; <i32> [#uses=1]
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%conv35 = trunc i32 %tmp34 to i16 ; <i16> [#uses=1]
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%tmp36 = load i16* null ; <i16> [#uses=1]
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%conv37 = trunc i16 %tmp36 to i8 ; <i8> [#uses=1]
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%tmp38 = load i32* %l_1128 ; <i32> [#uses=1]
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%conv39 = sext i32 %tmp38 to i64 ; <i64> [#uses=1]
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%tmp42 = load i32* %l_1129 ; <i32> [#uses=1]
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%conv43 = trunc i32 %tmp42 to i16 ; <i16> [#uses=1]
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%tmp44 = load i32* %l_1130 ; <i32> [#uses=1]
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%conv45 = sext i32 %tmp44 to i64 ; <i64> [#uses=1]
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%call46 = call i32 @func_18( i16 zeroext 0, i16 zeroext 0, i16 zeroext %tmp33, i16 zeroext %conv35, i8 zeroext %conv37, i64 %conv39, i32 0, i16 zeroext %conv43, i64 %conv45, i8 zeroext 1 ) ; <i32> [#uses=0]
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%call48 = call i32 @func_18( i16 zeroext 0, i16 zeroext 0, i16 zeroext 0, i16 zeroext 1, i8 zeroext 0, i64 0, i32 1, i16 zeroext %tmp28, i64 0, i8 zeroext 1 ) ; <i32> [#uses=0]
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%call50 = call i32 @func_18( i16 zeroext 1, i16 zeroext 0, i16 zeroext 0, i16 zeroext 1, i8 zeroext 0, i64 0, i32 1, i16 zeroext %conv19, i64 0, i8 zeroext 1 ) ; <i32> [#uses=0]
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ret i32 undef
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}
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declare i32 @func_18(i16 zeroext, i16 zeroext, i16 zeroext, i16 zeroext, i8 zeroext, i64, i32, i16 zeroext, i64, i8 zeroext)
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47
test/CodeGen/X86/anyext-uses.ll
Normal file
47
test/CodeGen/X86/anyext-uses.ll
Normal file
@ -0,0 +1,47 @@
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; RUN: llvm-as < %s | llc -march=x86-64 > %t
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; RUN: grep mov %t | count 8
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; RUN: not grep implicit %t
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; Avoid partial register updates; don't define an i8 register and read
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; the i32 super-register.
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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target triple = "x86_64-apple-darwin9.6"
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%struct.RC4_KEY = type { i8, i8, [256 x i8] }
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define void @foo(%struct.RC4_KEY* nocapture %key, i64 %len, i8* %indata, i8* %outdata) nounwind {
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entry:
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br label %bb24
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bb24: ; preds = %bb24, %entry
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%0 = load i8* null, align 1 ; <i8> [#uses=1]
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%1 = zext i8 %0 to i64 ; <i64> [#uses=1]
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%2 = shl i64 %1, 32 ; <i64> [#uses=1]
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%3 = getelementptr %struct.RC4_KEY* %key, i64 0, i32 2, i64 0 ; <i8*> [#uses=1]
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%4 = load i8* %3, align 1 ; <i8> [#uses=2]
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%5 = add i8 %4, 0 ; <i8> [#uses=2]
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%6 = zext i8 %5 to i64 ; <i64> [#uses=0]
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%7 = load i8* null, align 1 ; <i8> [#uses=1]
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%8 = zext i8 %4 to i32 ; <i32> [#uses=1]
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%9 = zext i8 %7 to i32 ; <i32> [#uses=1]
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%10 = add i32 %9, %8 ; <i32> [#uses=1]
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%11 = and i32 %10, 255 ; <i32> [#uses=1]
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%12 = zext i32 %11 to i64 ; <i64> [#uses=1]
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%13 = getelementptr %struct.RC4_KEY* %key, i64 0, i32 2, i64 %12 ; <i8*> [#uses=1]
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%14 = load i8* %13, align 1 ; <i8> [#uses=1]
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%15 = zext i8 %14 to i64 ; <i64> [#uses=1]
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%16 = shl i64 %15, 48 ; <i64> [#uses=1]
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%17 = getelementptr %struct.RC4_KEY* %key, i64 0, i32 2, i64 0 ; <i8*> [#uses=1]
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%18 = load i8* %17, align 1 ; <i8> [#uses=2]
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%19 = add i8 %18, %5 ; <i8> [#uses=1]
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%20 = zext i8 %19 to i64 ; <i64> [#uses=1]
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%21 = getelementptr %struct.RC4_KEY* %key, i64 0, i32 2, i64 %20 ; <i8*> [#uses=1]
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store i8 %18, i8* %21, align 1
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%22 = or i64 0, %2 ; <i64> [#uses=1]
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%23 = or i64 %22, 0 ; <i64> [#uses=1]
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%24 = or i64 %23, %16 ; <i64> [#uses=1]
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%25 = or i64 %24, 0 ; <i64> [#uses=1]
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%26 = xor i64 %25, 0 ; <i64> [#uses=1]
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store i64 %26, i64* null, align 8
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br label %bb24
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}
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34
test/CodeGen/X86/switch-zextload.ll
Normal file
34
test/CodeGen/X86/switch-zextload.ll
Normal file
@ -0,0 +1,34 @@
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; RUN: llvm-as < %s | llc -march=x86 | grep mov | count 1
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; Do zextload, instead of a load and a separate zext.
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
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target triple = "i386-apple-darwin9.6"
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%struct.move_s = type { i32, i32, i32, i32, i32, i32 }
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%struct.node_t = type { i8, i8, i8, i8, i32, i32, %struct.node_t**, %struct.node_t*, %struct.move_s }
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define fastcc void @set_proof_and_disproof_numbers(%struct.node_t* nocapture %node) nounwind {
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entry:
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%0 = load i8* null, align 1 ; <i8> [#uses=1]
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switch i8 %0, label %return [
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i8 2, label %bb31
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i8 0, label %bb80
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i8 1, label %bb82
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i8 3, label %bb84
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]
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bb31: ; preds = %entry
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unreachable
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bb80: ; preds = %entry
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ret void
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bb82: ; preds = %entry
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ret void
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bb84: ; preds = %entry
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ret void
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return: ; preds = %entry
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ret void
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}
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