RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-11-24 12:19:53 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

LiveIntervalAnalysis: Calculate liveness even if a superreg is reserved.

Browse Source 
A register unit may be allocatable and non-reserved but some of the
register(tuples) built with it are reserved. We still need to calculate
liveness in this case.

Note to out of tree targets: If you start seeing machine verifier errors
with this commit, it probably means that you do not properly mark super
registers of reserved register as reserved. See for example r292836 or
r292870 for example on how to fix that.

rdar://29996737

Differential Revision: https://reviews.llvm.org/D28881

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292871 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun 2017-01-24 01:12:58 +00:00
parent 71d3257864
commit 5862c98d09
2 changed files with 35 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -253,25 +253,32 @@ void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
// may share super-registers. That's OK because createDeadDefs() is
// idempotent. It is very rare for a register unit to have multiple roots, so
// uniquing super-registers is probably not worthwhile.
bool IsReserved = true;
for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
Super.isValid(); ++Super) {
unsigned Reg = *Super;
if (!MRI->reg_empty(Reg))
LRCalc->createDeadDefs(LR, Reg);
// A register unit is considered reserved if all its roots and all their
// super registers are reserved.
if (!MRI->isReserved(Reg))
IsReserved = false;
}
}
// Now extend LR to reach all uses.
// Ignore uses of reserved registers. We only track defs of those.
if (!IsReserved) {
for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
Super.isValid(); ++Super) {
unsigned Reg = *Super;
if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg))
if (!MRI->reg_empty(Reg))
LRCalc->extendToUses(LR, Reg);
}
}
}
// Flush the segment set to the segment vector.
if (UseSegmentSetForPhysRegs)

22
test/CodeGen/AArch64/live-interval-analysis.mir Normal file
View File

@ -0,0 +1,22 @@
# RUN: llc -o /dev/null %s -mtriple=aarch64-darwin-ios -run-pass=liveintervals -debug-only=regalloc -precompute-phys-liveness 2>&1 | FileCheck %s
# REQUIRES: asserts
--- |
define void @reserved_reg_liveness() { ret void }
...
---
# CHECK-LABEL: ********** INTERVALS **********
# W29 is reserved, so we should only see dead defs
# CHECK-DAG: W29 [0B,0d:{{[0-9]+}})[32r,32d:{{[0-9]+}})[64r,64d:{{[0-9]+}})
# For normal registers like x28 we should see the full intervals
# CHECK-DAG: W28 [0B,16r:{{[0-9]+}})[32r,48r:{{[0-9]+}})[48r,48d:{{[0-9]+}})
# CHECK: # End machine code for function reserved_reg_liveness.
name: reserved_reg_liveness
tracksRegLiveness: true
body: |
bb.0:
liveins: %x28_fp
%6 : xseqpairsclass = COPY %x28_fp
%x28_fp = COPY %6
%x28 = COPY %x28
%fp = COPY %fp
...