From 588158674572502daefbae5225715070274e6482 Mon Sep 17 00:00:00 2001
From: Akira Hatanaka <ahatanak@gmail.com>
Date: Fri, 9 Sep 2011 22:11:26 +0000
Subject: [PATCH] Make F31 and D15 non-reserved registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139420 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Mips/MipsRegisterInfo.cpp | 2 --
 lib/Target/Mips/MipsRegisterInfo.td  | 4 +---
 2 files changed, 1 insertion(+), 5 deletions(-)

diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp
index c12b3560ee6..bb06da9ac01 100644
--- a/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -129,8 +129,6 @@ getReservedRegs(const MachineFunction &MF) const {
   Reserved.set(Mips::SP);
   Reserved.set(Mips::FP);
   Reserved.set(Mips::RA);
-  Reserved.set(Mips::F31);
-  Reserved.set(Mips::D15);
 
   return Reserved;
 }
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td
index f0db518b754..9c288e48f54 100644
--- a/lib/Target/Mips/MipsRegisterInfo.td
+++ b/lib/Target/Mips/MipsRegisterInfo.td
@@ -182,9 +182,7 @@ def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
   // Not preserved across procedure calls
   D2, D3, D4, D5, D8, D9,
   // Callee save
-  D10, D11, D12, D13, D14,
-  // Reserved
-  D15)> {
+  D10, D11, D12, D13, D14, D15)> {
   let SubRegClasses = [(FGR32 sub_fpeven, sub_fpodd)];
 }