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Improve and elimination. On PPC, for:

Browse Source 
bool %test(int %X) {
        %Y = and int %X, 8
        %Z = setne int %Y, 0
        ret bool %Z
}

we now generate this:

        rlwinm r2, r3, 0, 28, 28
        srwi r3, r2, 3

instead of this:

        rlwinm r2, r3, 0, 28, 28
        srwi r2, r2, 3
        rlwinm r3, r2, 0, 31, 31

I'll leave it to Nate to get it down to one instruction. :)

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21391 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-04-21 06:28:15 +00:00
parent 1c2a9b95dc
commit 588bbbffa1
1 changed files with 26 additions and 6 deletions
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32
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -781,7 +781,7 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
case ISD::AND:
// (X & C1) & C2 == 0 iff C1 & C2 == 0.
if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
// FALL THROUGH
@ -792,9 +792,23 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
case ISD::SELECT:
return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
// TODO: (shl X, C1) & C2 == 0 iff (-1 << C1) & C2 == 0
// TODO: (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0
case ISD::SRL:
// (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
uint64_t NewVal = Mask << ShAmt->getValue();
SrcBits = MVT::getSizeInBits(Op.getValueType());
if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
}
return false;
case ISD::SHL:
// (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
uint64_t NewVal = Mask >> ShAmt->getValue();
return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
}
return false;
default: break;
}
@ -941,8 +955,14 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
if (MaskedValueIsZero(N1, C2, TLI)) // X and 0 -> 0
return getConstant(0, VT);
if (MaskedValueIsZero(N1, ~C2, TLI))
return N1; // if (X & ~C2) -> 0, the and is redundant
{
uint64_t NotC2 = ~C2;
if (VT != MVT::i64)
NotC2 &= (1ULL << MVT::getSizeInBits(VT))-1;
if (MaskedValueIsZero(N1, NotC2, TLI))
return N1; // if (X & ~C2) -> 0, the and is redundant
}
// FIXME: Should add a corresponding version of this for
// ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which