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AMDGPU: Delete dead code

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276675 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2016-07-25 19:06:25 +00:00
parent 568d841225
commit 5895e79530
4 changed files with 0 additions and 41 deletions
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8
lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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@ -55,14 +55,6 @@ EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32); return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
} }
EVT AMDGPUTargetLowering::getEquivalentBitType(LLVMContext &Ctx, EVT VT) {
unsigned StoreSize = VT.getStoreSizeInBits();
if (StoreSize <= 32)
return EVT::getIntegerVT(Ctx, StoreSize);
return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
}
AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM, AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
const AMDGPUSubtarget &STI) const AMDGPUSubtarget &STI)
: TargetLowering(TM), Subtarget(&STI) { : TargetLowering(TM), Subtarget(&STI) {

1
lib/Target/AMDGPU/AMDGPUISelLowering.h
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@ -75,7 +75,6 @@ protected:
SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
static EVT getEquivalentMemType(LLVMContext &Context, EVT VT); static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
static EVT getEquivalentBitType(LLVMContext &Context, EVT VT);
virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
SelectionDAG &DAG) const; SelectionDAG &DAG) const;

26
lib/Target/AMDGPU/AMDGPUSubtarget.cpp
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@ -193,19 +193,6 @@ SISubtarget::SISubtarget(const Triple &TT, StringRef GPU, StringRef FS,
TLInfo(TM, *this), TLInfo(TM, *this),
GISel() {} GISel() {}
unsigned R600Subtarget::getStackEntrySize() const {
switch (getWavefrontSize()) {
case 16:
return 8;
case 32:
return hasCaymanISA() ? 4 : 8;
case 64:
return 4;
default:
llvm_unreachable("Illegal wavefront size.");
}
}
void SISubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, void SISubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
unsigned NumRegionInstrs) const { unsigned NumRegionInstrs) const {
// Track register pressure so the scheduler can try to decrease // Track register pressure so the scheduler can try to decrease
@ -226,16 +213,3 @@ void SISubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
bool SISubtarget::isVGPRSpillingEnabled(const Function& F) const { bool SISubtarget::isVGPRSpillingEnabled(const Function& F) const {
return EnableVGPRSpilling || !AMDGPU::isShader(F.getCallingConv()); return EnableVGPRSpilling || !AMDGPU::isShader(F.getCallingConv());
} }
unsigned SISubtarget::getAmdKernelCodeChipID() const {
switch (getGeneration()) {
case SEA_ISLANDS:
return 12;
default:
llvm_unreachable("ChipID unknown");
}
}
AMDGPU::IsaVersion SISubtarget::getIsaVersion() const {
return AMDGPU::getIsaVersion(getFeatureBits());
}

6
lib/Target/AMDGPU/AMDGPUSubtarget.h
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@ -328,8 +328,6 @@ public:
short getTexVTXClauseSize() const { short getTexVTXClauseSize() const {
return TexVTXClauseSize; return TexVTXClauseSize;
} }
unsigned getStackEntrySize() const;
}; };
class SISubtarget final : public AMDGPUSubtarget { class SISubtarget final : public AMDGPUSubtarget {
@ -378,10 +376,6 @@ public:
bool isVGPRSpillingEnabled(const Function& F) const; bool isVGPRSpillingEnabled(const Function& F) const;
unsigned getAmdKernelCodeChipID() const;
AMDGPU::IsaVersion getIsaVersion() const;
unsigned getMaxNumUserSGPRs() const { unsigned getMaxNumUserSGPRs() const {
return 16; return 16;
} }