RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-12-14 23:48:49 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[ARM] Make testcase more explicit. NFC.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223841 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ahmed Bougacha 2014-12-09 22:08:57 +00:00
parent d9b12d3b11
commit 5898fd4260
1 changed files with 49 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

79
test/CodeGen/ARM/alloc-no-stack-realign.ll
View File

@ -8,21 +8,30 @@
define void @test1(<16 x float>* noalias sret %agg.result) nounwind ssp "no-realign-stack" {
entry:
; NO-REALIGN: test1
; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48
; NO-REALIGN: vst1.64
; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32
; NO-REALIGN: vst1.64
; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16
; NO-REALIGN: vst1.64
; NO-REALIGN: vst1.64
; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48
; NO-REALIGN: vst1.64
; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32
; NO-REALIGN: vst1.64
; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16
; NO-REALIGN: vst1.64
; NO-REALIGN: vst1.64
; NO-REALIGN-LABEL: test1
; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1:[0-9]+]]:128]
; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #48
; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1:[0-9]+]], #48
; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0:0]], #48
; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0]], #32
; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]
%retval = alloca <16 x float>, align 16
%0 = load <16 x float>* @T3_retval, align 16
store <16 x float> %0, <16 x float>* %retval
@ -33,22 +42,32 @@ entry:
define void @test2(<16 x float>* noalias sret %agg.result) nounwind ssp {
entry:
; REALIGN: test2
; REALIGN-LABEL: test2
; REALIGN: bic sp, sp, #63
; REALIGN: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48
; REALIGN: vst1.64
; REALIGN: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32
; REALIGN: vst1.64
; REALIGN: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16
; REALIGN: vst1.64
; REALIGN: vst1.64
; REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48
; REALIGN: vst1.64
; REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32
; REALIGN: vst1.64
; REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16
; REALIGN: vst1.64
; REALIGN: vst1.64
; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1:[0-9]+]]:128]
; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #48
; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; REALIGN: orr r[[R2:[0-9]+]], r[[R1:[0-9]+]], #48
; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; REALIGN: orr r[[R2:[0-9]+]], r[[R1]], #32
; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; REALIGN: orr r[[R2:[0-9]+]], r[[R1]], #16
; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
; REALIGN: add r[[R1:[0-9]+]], r[[R0:0]], #48
; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #32
; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #16
; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]
%retval = alloca <16 x float>, align 16
%0 = load <16 x float>* @T3_retval, align 16
store <16 x float> %0, <16 x float>* %retval